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GBZ43510-2023: Integrated circuit TSV 3D packaging reliability test methods guideline
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| Standard ID | Contents [version] | USD | STEP2 | [PDF] delivered in | Standard Title (Description) | Status | PDF |
| GB/Z 43510-2023 | English | 209 |
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Integrated circuit TSV 3D packaging reliability test methods guideline
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GB/Z 43510-2023
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Basic data | Standard ID | GB/Z 43510-2023 (GB/Z43510-2023) | | Description (Translated English) | Integrated circuit TSV 3D packaging reliability test methods guideline | | Sector / Industry | National Standard | | Classification of Chinese Standard | L55 | | Classification of International Standard | 31.200 | | Word Count Estimation | 10,164 | | Date of Issue | 2023-12-28 | | Date of Implementation | 2024-04-01 | | Issuing agency(ies) | State Administration for Market Regulation, China National Standardization Administration | GBZ43510-2023: Integrated circuit TSV 3D packaging reliability test methods guideline---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
GB /Z 43510-2023: Guide to reliability test methods for TSV three-dimensional packaging of integrated circuits
ICS 31:200
CCSL55
National Standardization Guiding Technical Documents of the People's Republic of China
Integrated circuit TSV three-dimensional packaging reliability
Test Method Guide
Published on 2023-12-28
2024-04-01 Implementation
State Administration for Market Regulation
Released by the National Standardization Administration Committee
Foreword
This document complies with the provisions of GB/T 1:1-2020 "Standardization Work Guidelines Part 1: Structure and Drafting Rules of Standardization Documents"
Drafting:
Please note that some content in this document may be subject to patents: The publisher of this document assumes no responsibility for identifying patents:
This document is proposed by the Ministry of Industry and Information Technology of the People's Republic of China:
This document is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78):
This document was drafted by: China Electronics Technology Standardization Institute, University of Electronic Science and Technology of China, Huajin Semiconductor Packaging Leading Technology R&D Center
Co:, Ltd:, the 771st Research Institute of the Ninth Research Institute of China Aerospace Science and Technology Corporation, the Fifth Research Institute of Electronics of the Ministry of Industry and Information Technology, China
Institute of Microelectronics, Academy of Sciences, Institute of Semiconductor, Chinese Academy of Sciences:
The main drafters of this document: Li Kun, Peng Bo, Xiao Kelati, Wu Daowei, Zhou Bin, Gao Jiantou, and Li Wenchang:
Integrated circuit TSV three-dimensional packaging reliability
Test Method Guide
1 Scope
This document provides guidance on reliability test methods for process development and verification of through silicon via (TSV) three-dimensional packaging:
This document is applicable to the process verification of TSV three-dimensional packaging manufactured using three process processes: through-hole first, middle through-hole and through-last:
test:
2 Normative reference documents
The contents of the following documents constitute essential provisions of this document through normative references in the text: Among them, the dated quotations
For undated referenced documents, only the version corresponding to that date applies to this document; for undated referenced documents, the latest version (including all amendments) applies to
this document:
GB/T 4937:4 Mechanical and climatic test methods for semiconductor devices Part 4: Highly accelerated steady-state hot and humid test (HAST)
GB/T 4937:11 Mechanical and climatic test methods for semiconductor devices Part 11: Rapid temperature change double liquid bath method
GB/T 4937:20 Mechanical and climatic test methods for semiconductor devices - Part 20: Resistance of plastic-encapsulated surface-mounted devices to moisture and soldering
Comprehensive impact of heating
GB/T 4937:23 Mechanical and climatic test methods for semiconductor devices Part 23: High temperature operating life
GB/T 4937:30 Mechanical and climatic test methods for semiconductor devices Part 30: Reliability of non-sealed surface-mounted devices
Pretreatment before test
GB/T 4937:42 Mechanical and climatic test methods for semiconductor devices Part 42: Temperature and humidity storage
GB/T 12750 Semiconductor device integrated circuits Part 11: Specifications for semiconductor integrated circuits (excluding hybrid circuits)
IEC 60749-5 Mechanical and climatic test methods for semiconductor devices Part 5: Steady-state temperature and humidity bias life test (Semi-
biaslifetest)
IEC 60749-24 Mechanical and climatic test methods for semiconductor devices Part 24: Unbiased strongly accelerated steady-state damp heat test
ance-UnbiasedHAST)
IEC 60749-29 Mechanical and climatic test methods for semiconductor devices Part 29: Latch-up test (Semiconductor
IEC 62374 Time-dependent (electrical) dielectric breakdown (TDDB) test of gate dielectric layer of semiconductor devices [Semiconductorde-
grationtest)
3 Terms and definitions
The following terms and definitions apply to this document:
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