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GB/T 32814-2016: Silicon-based MEMS fabrication technology -- Specification for criterion of the SOI wafer based MEMS process
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| Standard ID | Contents [version] | USD | STEP2 | [PDF] delivered in | Standard Title (Description) | Status | PDF |
| GB/T 32814-2016 | English | 279 |
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Silicon-based MEMS fabrication technology -- Specification for criterion of the SOI wafer based MEMS process
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GB/T 32814-2016
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Basic data | Standard ID | GB/T 32814-2016 (GB/T32814-2016) | | Description (Translated English) | Silicon-based MEMS fabrication technology -- Specification for criterion of the SOI wafer based MEMS process | | Sector / Industry | National Standard (Recommended) | | Classification of Chinese Standard | L55 | | Classification of International Standard | 31.200 | | Word Count Estimation | 14,120 | | Date of Issue | 2016-08-29 | | Date of Implementation | 2017-03-01 | | Regulation (derived from) | National Standard Announcement 2016 No.14 | | Issuing agency(ies) | General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China, Standardization Administration of the People's Republic of China | GB/T 32814-2016: Silicon-based MEMS fabrication technology -- Specification for criterion of the SOI wafer based MEMS process
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Silicon-based MEMS fabrication technology - Specification for criterion SOR wafer based MEMS process
ICS 31.200
L55
National Standards of People's Republic of China
Silicon-based MEMS manufacturing technology
MEMS Technology Specification Based on SOI Wafer
2016-08-29 released
2017-03-01 implementation
General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China
China National Standardization Management Committee released
Directory
Preface I
1 Scope 1
2 normative reference document 1
3 Terms and definitions 1
4 Process 1
4.1 Overview 1
4.2 wafer cleaning 2
4.3 Preparation of the mask 2
4.4 Dry etching 4
4.5 Structure Release 5
4.6 wafers to mask 7
5 process processing capacity 7
5.1 Process capability requirements 7
5.2 Process stability requirements 8
6 process requirements 8
6.1 Personnel requirements 8
6.2 Environmental requirements 8
6.3 Equipment requirements 8
7 Requirements for raw materials and auxiliary materials 9
8 Safety and Environmental Requirements 9
8.1 Security 9
8.2 Chemical reagents 10
8.3 Emissions 10
9 test 10
9.1 General 10
9.2 Critical Process Inspection
9.3 Final inspection 11
Foreword
This standard is drafted in accordance with the rules given in GB/T 1.1-2009.
This standard by the National Microelectromechanical Technology Standardization Technical Committee (SAC/TC336) proposed and centralized.
The main drafting of this standard. Northwestern Polytechnical University, in the machine productivity promotion center.
The main drafters of this standard. Yuan Weizheng, Xie Jianbing, Li Haibin, Qiao Dayong, Ma Zhibo, Chang Honglong, Liu Wei.
Silicon-based MEMS manufacturing technology
MEMS Technology Specification Based on SOI Wafer
1 Scope
This standard specifies the process requirements and quality inspection requirements that should be followed when processing MEMS devices using SOI wafers.
This standard is applicable to the processing and quality inspection of silicon devices based on SOI wafers in silicon-based MEMS manufacturing technology.
2 normative reference documents
The following documents are indispensable for the application of this document. For dated references, only the dated edition applies to this article
Pieces. For undated references, the latest edition (including all modifications) applies to this document.
GB/T 26111 terminology for microelectromechanical systems (MEMS)
Code for design of clean building of GB 50073
3 terms and definitions
GB/T 26111 Definitions and the following terms and definitions apply to this document.
3.1
Silicon on the insulator on the insulator; SOI
In the middle of the two layers of silicon to introduce a layer of oxide layer, forming a "silicon - silica - silicon" sandwich structure of the technology. Which top silicon said
For the device layer (devicelayer), the underlying silicon is called the substrate layer (handlelayer), the silicon dioxide layer is called buried layer (buriedlayer).
Note. The current techniques for preparing SOI wafers include separation of implantation of oxygen (SIMOX) technology, silicon bonding and backside thinning
(bondingSOI, BSOI) technology and the combination of bonding and injection of intelligent stripping (smartcut) technology.
3.2
Release releasing
So that the movable part of the MEMS structure and the rest of the separation, so that the process of moving.
3.3
Deep Reactive Ion Etching Deepreactivelonetching;
A reactive ion etching method with a high aspect ratio, typically using an inductively coupled plasma (inductivelycoupled plasma,
ICP) etching, sometimes referred to as ICP etching.
3.4
footing effect footingeffect
SOI silicon wafer in the deep reactive ion etching process, when the etching to reach the buried layer, the occurrence of lateral etching phenomenon.
4 process flow
4.1 Overview
MEMS processes based on SOI wafers include mask preparation, dry etching, structural release, etc., as shown in Figure 1, where
The key process is represented by (G).
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