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GB/T 41033-2021 English PDF

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GB/T 41033-2021: Design requirements of radiation hardening for CMOS IC
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Basic data

Standard ID GB/T 41033-2021 (GB/T41033-2021)
Description (Translated English) Design requirements of radiation hardening for CMOS IC
Sector / Industry National Standard (Recommended)
Classification of Chinese Standard V29
Word Count Estimation 18,112
Issuing agency(ies) State Administration for Market Regulation, China National Standardization Administration

GB/T 41033-2021: Design requirements of radiation hardening for CMOS IC

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Design requirements of radiation hardening for CMOS ICs ICS 49:035 CCSV29 National Standards of People's Republic of China Radiation hardening design requirements for CMOS integrated circuits Published on 2021-12-31 2022-07-01 Implementation State Administration for Market Regulation Released by the National Standardization Administration directory Preface I 1 Scope 1 2 Normative references 1 3 Terms, Definitions and Abbreviations 1 3:1 Terms and Definitions 1 3:2 Abbreviations 2 4 Design Process 2 5 Radiation hardening design requirements 3 5:1 Design principles and requirements for anti-total dose radiation reinforcement 3 5:2 Design principles and requirements for anti-single-event radiation hardening 7 6 Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits 10 6:1 General Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits 10 6:2 Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits 10 6:3 Modeling and Simulation Methods for Radiation Effects of Integrated Circuits 10 7 Irradiation verification test requirements 11 7:1 Requirements for total dose irradiation verification test 11 7:2 Single particle irradiation verification test requirements 14

foreword

This document is in accordance with the provisions of GB/T 1:1-2020 "Guidelines for Standardization Work Part 1: Structure and Drafting Rules of Standardization Documents" drafted: Please note that some content of this document may be patented: The issuing agency of this document assumes no responsibility for identifying patents: This document is proposed and managed by the National Standardization Technical Committee of Aerospace Technology and Its Application (SAC/TC425): This document is drafted by: The No: 771 Research Institute of the Ninth Research Institute of China Aerospace Science and Technology Corporation: The main drafters of this document: Liu Zhi, Ge Mei, Xie Chengmin, Wang Bin, Yu Hongbo, Yue Hongju, Yao Siyuan, Li Haisong, Geng Zengjian, Hu Qiaoyu: Radiation hardening design requirements for CMOS integrated circuits

1 Scope

This document specifies the process, design requirements, modeling and simulation, verification and design of CMOS integrated circuits for radiation resistance (total dose, single event) hardening design: verification test requirements: This document applies to digital integrated circuits, analog integrated circuits and digital-analog hybrid integrated circuits based on bulk silicon/SOICMOS process: Radiation-resistant (total dose, single particle) rugged design:

2 Normative references

The contents of the following documents constitute essential provisions of this document through normative references in the text: Among them, dated citations documents, only the version corresponding to that date applies to this document: For undated references, the latest edition (including all amendments) applies to this document: GB/T 9178 Integrated Circuit Terminology 3 Terms, Definitions and Abbreviations 3:1 Terms and Definitions The terms and definitions defined in GB/T 9178 and the following apply to this document: 3:1:1 totalionizingdoseeffects; TID The total dose radiation effect refers to the phenomenon that the accumulation of ionizing radiation leads to the degradation of the parameters of the device: 3:1:2 single event effects; SEE A single heavy ion or proton with a certain energy is injected into the integrated circuit, causing the integrated circuit to flip, lock, burn, etc:, resulting in the integrated circuit A general term for the phenomenon of performance degradation or functional failure: 3:1:3 singleeventupseteffects; SEU Effects of changes in the logic state of integrated circuits induced by single-event radiation: 3:1:4 singleeventtransienteffects;SET The effect of an abnormal pulse signal at the output of an integrated circuit caused by single-event radiation: 3:1:5 Single event latch-up effects; SEL The effect of integrated circuit latch-up caused by single event radiation: 3:1:6 Design reinforcement radiationhardeningbydesign; RHBD The technology of improving the radiation resistance of semiconductor devices or integrated circuits by designing circuit topology and layout structure with radiation resistance:

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