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SJ 20954-2006 English PDF

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SJ 20954-2006: Integrated circuits latch-up test
Status: Valid
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SJ 20954-2006English479 Add to Cart 3 days [Need to translate] Integrated circuits latch-up test Valid SJ 20954-2006

PDF similar to SJ 20954-2006


Standard similar to SJ 20954-2006

SAMR 76   SJ/T 11460.6.4   GB/T 35010.6   SJ 21473.7   SJ 21614   SJ 21473.6   

Basic data

Standard ID SJ 20954-2006 (SJ20954-2006)
Description (Translated English) Integrated circuits latch-up test
Sector / Industry Electronics Industry Standard
Classification of Chinese Standard L55
Classification of International Standard 31.200
Word Count Estimation 15,189
Date of Issue 2006-08-07
Date of Implementation 2006-12-30
Quoted Standard GB/T 17574
Issuing agency(ies) Ministry of Industry and Information Technology
Summary This standard specifies the integrated circuit (IC) of the current lockout and overvoltage lockout of test methods. This standard applies to create a test IC lock test method used to determine the IC locking feature and make sure the lock failure criterion. Lock sensitivity for determining product reliability, minimum no failure rate (NTF) and over electrical stress failure (EOS) is very important. This test method is applicable to NMOS, CMOS, bipolar and a variety of products using such processes. When the device is placed in the test method appears locked, indicating failure of the electrical properties of the device, independent of the special structure of the device.

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