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Electronics assembly technology - Part 4: Endurance test methods for solder joint of area array type package surface mount devices
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GB/T 45713.4-2025
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Basic data Standard ID | GB/T 45713.4-2025 (GB/T45713.4-2025) | Description (Translated English) | Electronics assembly technology - Part 4: Endurance test methods for solder joint of area array type package surface mount devices | Sector / Industry | National Standard (Recommended) | Classification of Chinese Standard | L30 | Classification of International Standard | 31.180 | Word Count Estimation | 38,382 | Date of Issue | 2025-05-30 | Date of Implementation | 2025-09-01 | Issuing agency(ies) | State Administration for Market Regulation, China National Standardization Administration |
GB/T 45713.4-2025: Electronics assembly technology - Part 4: Endurance test methods for solder joint of area array type package surface mount devices ---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
ICS 31.180
CCSL30
National Standard of the People's Republic of China
Electronic assembly technology Part 4.Array packaging
Durability test method for solder joints of surface mounted devices
(IEC 62137-4.2014,MOD)
Released on 2025-05-30
2025-09-01 Implementation
State Administration for Market Regulation
The National Standardization Administration issued
Table of contents
Preface III
Introduction IV
1 Scope 1
2 Normative references 1
3 Terms, definitions and abbreviations 2
4 General requirements 2
5 Test equipment and materials 3
6 Sample preparation 4
7 Temperature cycle test 5
8 Temperature cycle life 7
9 Items specified in relevant product specifications 7
Appendix A (Informative) Electrical continuity test of package solder joints 8
Appendix B (Informative) Reflow solderability test method for packaged devices and test board pads 10
Appendix C (Informative) Test Board Design Guide 14
Appendix D (Informative) Heat resistance of test board reflow soldering 17
Appendix E (Informative) Test board pad pull-off strength measurement method 19
Appendix F (Informative) Standard Installation Process for Packaged Devices 22
Appendix G (Informative) Mechanical stress of packaged devices 25
Appendix H (Informative) Accelerated Temperature Cycle Test of Solder Joints 26
Reference 31
Figure 1 Durability test evaluation area 3
Figure 2 Typical reflow curve of Sn63Pb37 solder alloy 4
Figure 3 Typical reflow soldering curve of Sn96.5Ag3Cu0.5 solder alloy
Figure 4 Test conditions for temperature cycle test 6
Figure A.1 Circuit example for solder joint electrical continuity test 8
Figure A.2 Example of continuous monitoring resistance measurement during temperature cycle test 9
Figure B.1 Temperature measurement of sample using thermocouple 11
Figure B.2 Solder rejection caused by contaminants on solder ball surface 12
Figure B.3 Solder ball detached from the device body 12
Figure C.1 Standard pad shape of the test board 16
Figure E.1 Measurement method of pull-off strength 20
Figure F.1 Example of solder paste printing conditions 23
Figure F.2 Thermocouple temperature measurement 23
Figure H.1 FBGA package device and FEA model used to calculate acceleration factor 28
Figure H.2 Example of acceleration factor (AF) for FBGA packaged device with Sn96.5Ag3Cu0.5 solder alloy 29
Figure H.3 Fatigue properties of Sn96.5Ag3Cu0.5 alloy micro solder joints (Nf = load reduction of 20% under initial load) 30
Table 1 Test conditions for temperature cycle test 6
Table C.1 Classification of test panel types 14
Table C.2 Standard configuration of test board layers 15
Table F.1 Design criteria for printed modules used for encapsulated devices 22
Table G.1 Mechanical stress of array package components after installation 25
Table H.1 Example of acceleration factor test results (Sn63Pb37 solder alloy) 26
Table H.2 Example of acceleration factor test results (Sn96.5Ag3Cu0.5 solder alloy) 28
Table H.3 Material constants and inelasticity of FBGA packaged devices (Sn96.5Ag3Cu0.5 solder alloy) calculated by FEA
Strain range 29
Foreword
This document is in accordance with the provisions of GB/T 1.1-2020 "Guidelines for standardization work Part 1.Structure and drafting rules for standardization documents"
Drafting.
This document is Part 4 of GB/T 45713 Electronic Assembly Technology. GB/T 45713 has been published in the following parts.
--- Part 4.Durability test method for solder joints of array type package surface mount devices.
This document is modified to adopt IEC 62137-4.2014 "Electronic assembly technology Part 4.Resistance to corrosion of solder joints of array-type package surface mount devices"
Durability Test Methods.
This document has made the following structural adjustments compared to IEC 62137-4.2014.
---Appendix A, Appendix B, Appendix C, Appendix D, Appendix E, Appendix F, Appendix G, Appendix H correspond to IEC 62137-4.2014
Appendix B, Appendix C, Appendix D, Appendix E, Appendix F, Appendix G, Appendix H, Appendix A.
The technical differences between this document and IEC 62137-4.2014 and their reasons are as follows.
--- The normative reference GB/T 2423.22 replaces IEC 60068-2-14 (see 5.3, 7.3) to adapt to my country's technical conditions.
Increase operability;
--- Deleted IEC 60194 (see 3.1 of IEC 62137-4.2014) because the standard has been abolished;
--- The abbreviation "CGA" (see 3.2 of IEC 62137-4.2014) has been deleted because the term is not mentioned in the text;
--- Replace the "instantaneous interruption detector" (see 7.2, 7.3, 7.6) with the "resistance recorder" and supplement the measurement method of the equipment;
--- Added "The daisy chain circuit is recommended to be placed on the top layer of the breadboard, and it is recommended to place a
Multiple measurement pads are drawn between different nodes in the circuit" [see 5.5c)] to facilitate the rapid location of solder joint failure;
---In "Sample Preparation", "and use a stainless steel template with a thickness of 120μm to 150μm to print solder paste onto the test board pads
" and use a stainless steel template of appropriate thickness (suitable for reflow soldering process) to print the solder paste onto the pads of the test board"
[See 6a)] to adapt to solder paste printing of smaller pitch array packaging devices.
The following editorial changes were made to this document.
--- Added defect inspection item "Solder voids exceeding product specification requirements" in "Re-inspection" (see F.3.6) to avoid interference from solder voids
Fatigue life.
Please note that some of the contents of this document may involve patents. The issuing organization of this document does not assume the responsibility for identifying patents.
This document was proposed by the Ministry of Industry and Information Technology of the People's Republic of China.
This document is under the jurisdiction of the National Printed Circuit Standardization Technical Committee (SAC/TC47).
This document was drafted by. China Electronics Technology Group Corporation 36th Research Institute, China Electronics Technology Standardization Institute, China Aerospace Science and Industry Corporation
The 8358th Institute of the Third Research Institute of the Group and China Certification and Inspection (Jiangsu) Testing Technology Co., Ltd.
The main drafters of this document are. Jin Dayuan, Xie Xin, Cao Yi, Ye Wei, Zhang Naihong, Wan Yun, He Minxian, Wang Chengshan, Qiao Guojun, Wu Chenjun,
Chai Guanghui, Xue Chao.
Introduction
Array-type package surface mount devices are widely used in modern electronic devices, from high-performance computers to portable smart terminals.
The durability of electronic devices is crucial to their reliability and service life. Electronic assembly technology covers the process of assembling electronic components to printing.
A series of processes and methods on circuit boards, and related standards are of great significance to ensure product quality. GB/T 45713 "Electronic Assembly Technology" is proposed by
It consists of two parts.
--- Part 3.Guidance for the selection of soldering environment and durability test methods. The purpose is to guide surface mount devices (SMD),
Selection of reliability test methods for solder joints of array devices, pin devices and plug-in devices with different solder alloys.
--- Part 4.Durability test method for solder joints of array type package surface mount devices. It is intended for use in industrial and consumer fields.
Array package devices (FBGA, BGA, FLGA and LGA) and leadless
Evaluation and testing of solder joint durability of type package devices (SON, QFN).
This document deals with the specific requirements for the durability test method of solder joints of array type package surface mount devices.
The durability performance in actual use provides a basis to ensure the stable operation of electronic equipment under complex working conditions.
Electronic assembly technology Part 4.Array packaging
Durability test method for solder joints of surface mounted devices
1 Scope
This document specifies the durability test method for solder joints of array-type packaged devices mounted on printed boards to evaluate the resistance of solder joints to thermal mechanical stress.
Durability of force.
This document applies to array-type package devices (FBGA,
Evaluation and testing of solder joint durability of BGA, FLGA and LGA) and leadless package devices (SON, QFN), not applicable to semiconductor
Evaluation and testing of the device's own performance.
2 Normative references
The contents of the following documents constitute essential clauses of this document through normative references in this document.
For referenced documents without a date, only the version corresponding to that date applies to this document; for referenced documents without a date, the latest version (including all amendments) applies to
This document.
GB/T 2423.22 Environmental testing Part 2.Test method Test N. Temperature change (GB/T 2423.22-2012,
IEC 60068-2-14.2009, IDT)
IEC 60191-6-2 Mechanical standardization of semiconductor devices Part 6-2.Surface mount semiconductor device package outline drawing
General Rules Design Guidelines for 1.50mm, 1.27mm, and 1.00mm Pitch Ball and Post Terminal Packages (Mechanicalstand-
IEC 60191-6-5 Mechanical standardization of semiconductor devices Part 6-5.Drawing of the outline of the package of surface mount semiconductor devices
IEC 61190-1-3 Auxiliary materials for electronic assemblies Part 1-3.Electronic grade brazing alloys and fluxed and solderless brazing alloys for electronic soldering
IEC 61249-2-7 Materials for printed boards and other interconnect structures Part 2-7.Coated and uncoated reinforced substrates specifies the
IEC 61249-2-8 Materials for printed boards and other interconnect structures Part 2-8.Coated and uncoated reinforced substrates specifies the
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