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GB/T 35006-2018 English PDF

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GB/T 35006-2018: Semiconductor integrated circuits -- Measuring method of level converter
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Basic data

Standard ID GB/T 35006-2018 (GB/T35006-2018)
Description (Translated English) Semiconductor integrated circuits -- Measuring method of level converter
Sector / Industry National Standard (Recommended)
Classification of Chinese Standard L56
Classification of International Standard 31.200
Word Count Estimation 30,321
Date of Issue 2018-03-15
Date of Implementation 2018-08-01
Issuing agency(ies) State Administration for Market Regulation, China National Standardization Administration

GB/T 35006-2018: Semiconductor integrated circuits -- Measuring method of level converter

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Semiconductor integrated circuits--Measuring method of level converter ICS 31.200 L56 National Standards of People's Republic of China Semiconductor integrated circuit Level converter test method Published by.2018-03-15 2018-08-01 Implementation General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China China National Standardization Administration released Directory Preface III 1 Scope 1 2 Normative references 1 3 Terms and Definitions 1 4 General 2 4.1 Test Environment Requirements 2 4.2 Test Considerations 2 5 Functional Test 2 5.1 Purpose 2 5.2 Test principle diagram 2 5.3 Test Procedure 3 5.4 Test Condition 3 6 Static Parameter Test 3 6.1 Input Clamping Voltage (VIK) 3 6.2 Input High Level Voltage (VIH) 4 6.3 Input Low Level Voltage (VIL) 5 6.4 Output High Voltage (VOH) 5 6.5 Output Low-Voltage (VOL) 5 6.6 Input High Level Current (IIH) 5 6.7 Input Low Current (IIL) 5 6.8 Output High-Level Current (IOH) 5 6.9 Output Low-Level Current (IOL) 6 6.10 High-level Current Output in High-Z (IOZH) 7 6.11 Output Low-Z Current (IOZL) at High Impedance 8 6.12 Quiescent Current (ICCQ) 9 6.13 Current Offset (ΔICCQ) 9 6.14 Output Ground Short Circuit Current (IOSL) 10 6.15 Output Short-to-Supply Current (IOSH) 11 6.16 Turn on Resistance (RON) 12 6.17 Channel Offset Resistance (ΔRON) 13 7 Dynamic Parameter Test 14 7.1 Supply Current (ICC) 14 7.2 Maximum operating frequency (fMAX) 14 7.3 Minimum operating frequency (fMIN) 15 7.4 Input Capacitor (CI) and Output Capacitor (CO) 16 7.5 Output from Low Level to High Level Transmission Delay (tPLH) 16 7.6 Output High to Low Transmission Delay (tPHL) 17 7.7 Output Transmission Delay from High-Z to High-Level (tPZH) 18 7.8 Output from High Impedance to Low Transmission Delay (tPZL) 18 7.9 Output from High Level to High Impedance Transmission Delay (tPHZ) 19 7.10 Output from Low Level to High Impedance Transmission Delay (tPLZ) 20 7.11 Output Transition from Low Level to High Level (tTLH) 21 7.12 Output Transition from High Level to Low Level (tTHL) 22 7.13 Eye Height (eH) 23 7.14 Eye Width (eW) 24 7.15 Deterministic Jitter (Dj) 25 7.16 Random Jitter (Rj) 25 7.17 Total Jitter 26

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009. Please note that some of the contents of this document may involve patents. The issuing agency of this document does not assume responsibility for identifying these patents. This standard was proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This standard is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee IC Subcommittee (SAC/TC78/SC2). This standard was drafted by Shenzhen Microelectronics Co., Ltd., the 58th Institute of China Electronics Technology Corporation, industry and information Ministry of Electronics Fifth Institute, Chengdu Zhenxin Technology Co., Ltd. The main drafters of this standard. Yan Chengyong, Yan Haizhong, Lu Jian, Wei Jun, Wang Xiaoqiang, and Luo Bin. Semiconductor integrated circuit Level converter test method

1 Scope

This standard specifies the test methods for the function, static parameters and dynamic parameters of a semiconductor integrated circuit level shifter (hereinafter referred to as a device). This standard applies to the test of the function, static parameters and dynamic parameters of the level converter of semiconductor integrated circuits.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this article Pieces. For undated references, the latest version (including all amendments) applies to this document. GB/T 17574-1998 Semiconductor device integrated circuit Part 2. Digital integrated circuits

3 Terms and definitions

The following terms and definitions apply to this document. 3.1 Device under test deviceundertest; DUT Tested object during the test. 3.2 Test adapter board loadboard Adapter plate or application test board for the connection of the device under test to the automatic test system (ATE). 3.3 Reference level referencevoltage During the test, a threshold level inherent to the input and output devices of the test system was tested. 3.4 Eye diagram eyediagram The result of the bit stream of the collected serial signal is cumulatively displayed in an afterglow manner. The superimposed figure is an eyelet. 3.5 Eye height eyeheight The amplitude of the eye opening in the vertical direction. 3.6 Eye width width The amplitude of the eye opening in the horizontal direction. 3.7 Jitter jitter The short-term deviation of the signal at a certain moment relative to its ideal time position.

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