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GB/T 35004-2018 English PDF

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GB/T 35004-2018: Logic digital integrated circuits -- Specification for I/O interface model for integrated circuit
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Basic data

Standard ID GB/T 35004-2018 (GB/T35004-2018)
Description (Translated English) Logic digital integrated circuits -- Specification for I/O interface model for integrated circuit
Sector / Industry National Standard (Recommended)
Classification of Chinese Standard L56
Classification of International Standard 31.200
Word Count Estimation 62,638
Date of Issue 2018-03-15
Date of Implementation 2018-08-01
Issuing agency(ies) State Administration for Market Regulation, China National Standardization Administration

GB/T 35004-2018: Logic digital integrated circuits -- Specification for I/O interface model for integrated circuit


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Logic digital integrated circuits--Specification for I/O interface model for integrated circuit ICS 31.200 L56 National Standards of People's Republic of China Digital integrated circuit input/output electrical interface Model specification (IEC /T S62404.2007, IDT) Published on.2018-03-15 2018-08-01 implementation General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China China National Standardization Administration issued

Content

Foreword III Introduction IV 1 Scope 1 2 Normative references 1 3 Terms and Definitions 1 4 General 1 4.1 Overview 1 4.2 Model coverage 2 4.3 Circuit Language 2 4.4 Device Model 2 4.5 Model Structure 2 4.6 Simulation 2 4.7 Association with IBIS 2 5 Model structure 3 6 Detailed Model Description 6 6.1 Description Rule 6 6.2 IC model file 8 6.3 Package Model File 31 6.4 Module Model File 38 7 model level 44 Appendix A (informative) Model release process 46 Appendix B (informative) Example of model file description 47 B.1 Introduction 47 B.2 chip structure and its equivalent circuit 47 B.3 Description Example 47

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009. This standard uses the translation method equivalent to IEC /T S62404.2007 "Digital Integrated Circuit Input/Output Electrical Interface Model Specification". Please note that some of the contents of this document may involve patents. The issuing organization of this document is not responsible for identifying these patents. This standard was proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This standard is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee Integrated Circuit Subcommittee (SAC/TC78). This standard was drafted. Electronic Fifth Institute of the Ministry of Industry and Information Technology, Institute of Microelectronics, Chinese Academy of Sciences, Shenzhen Guowei Electronics. The main drafters of this standard. He Chunhua, Hou Bo, Ten Rui, Shi Qian, En Yunfei, Liu Miao, Lei Dengyun, Yan Fang, Yu Zhaojie, Liang Shizhang.

Introduction

With the rapid growth of electronic systems, accurate predictions of electrical performance, including the noise of integrated circuit electronic systems, are becoming more and more important. Although an emulator can be used to predict the electrical performance of an electronic system, it is necessary to be able to accurately describe the electrical characteristics of the integrated circuit. Sexual model. Users require semiconductor manufacturers/suppliers to provide corresponding device models for different simulation tools, however some of these models Not compatible with SPICE. Since the SPICE model contains specific process parameters, it is necessary to sign a non-public agreement with the seller to obtain These parameters. Existing integrated circuit models. IBIS (Input/Output Buffer Interface Specification, approval number IEC 62014-1) has the following characteristics. ● The electrical characteristics of the I/O buffer are described in tabular form, so that specific information disclosed, such as process parameters, can be significantly reduced. ● It is easy to get an IBIS model that is compatible with multiple simulation tools. ● Open source tools that convert SPICE models into IBIS models. However, the IBIS model has the following problems. ● The current and ground current models are not accurately used for power and ground bounce analysis. ● Since the IBIS model has only input and output phases, it is difficult to establish the impact of the load on the board based on the input and output waveforms. model. The fixed model of IBIS is not suitable for flexible description of other circuit systems. ● In order to accurately simulate EMI characteristics, more information such as material constants and three-dimensional structures is required. Digital integrated circuit input/output electrical interface Model specification

1 Scope

In order to provide a standard for the analysis of the electrical characteristics of the device, the following items need to be considered to make the input signal and output signal of the integrated circuit Standardization of electrical models for numbers, power supplies, and ground ports. a) Standardize on existing standards to address existing problems and expand analytical capabilities. b) Define more flexible description rules for electronic circuits to provide more accurate PCB analysis. c) Introduce a modeling level concept to provide relevant data for each application. d) Improve the electrical model of the package and module.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this article. Pieces. For undated references, the latest edition (including all amendments) applies to this document. IEC 62014-1.2001 Electronic Design Automation Library Part 1. Input/Output Buffer Information Specification (Electronicdesign automationlibraries-Part 1. Input/outputbufferinformationspecifications) (IBIS version 3.2)

3 Terms and definitions

Under consideration.

4 General

4.1 Overview The interface model diagram is shown in Figure 1. Figure 1 interface model diagram 4.2 Model coverage The circuit described by the model covers some or all of the input/output buffers and packages. 4.3 Circuit Language The circuit should be described as an extended SPICE structure. This architecture allows simple buffers, complex buffers, and power supplies to be described in a uniform format. And ground, package and complex memory modules. 4.4 device model The characteristics of a nonlinear device are described in a one-, two-, or three-dimensional form file. 4.5 Model structure The model's data includes the integrated circuit, package, and module sections. Therefore, each part can be generated independently. 4.6 Simulation The printed circuit board's netlist and the input/output buffer model defined by the specification provide accurate circuit simulation results. 4.7 Association with IBIS It is beneficial to further develop tools for extracting IBIS data.

5 model structure

The model should describe the internals, packages, and modules of the IC, as shown in Figure 2. The components of the IC, package and module model are shown in Table 1. The IC, package and module data structures are shown in Figure 3, Figure 4, and Figure 5, respectively. Figure 2 Levels of the three models Table 1 Components of the model framework File component description IC model file Title IC type, model version, model level External terminal of the external port IC (package line) Pad layout IC pad connection to internal port Circuit description internal circuit and connection Input excitation distributes internal circuitry and excitation produces output waveforms Input excitation input waveform Device model Characteristics of nonlinear devices in one-, two-, and three-dimensional table data. Nonlinear device Such as triodes, diodes, etc. The package model name used by the package model reference Package model file Title package name, model version, model level Model name package model model list Inter-comparison of internal port internal ports and package internal circuit models External port external circuit and package internal circuit model Circuit description internal circuit and its connection Device Model The characteristics of nonlinear devices in one-, two-, and three-dimensional table data. Nonlinear devices such as transistors, diodes, etc. Structural material, location and three-dimensional structure Module model file Title module name, model version, model level External port of the external port module (lead end) Circuit description internal circuit and its connection Signal source internal circuits and ports generate output waveforms on the corresponding external ports Device Model The characteristics of nonlinear devices in one-, two-, and three-dimensional table data. Nonlinear devices such as transistors, diodes, etc. IC module model reference IC/module model file and model name used Structural material, location and three-dimensional structure Figure 3 Data structure of the IMIC model file of the IC Figure 4 Data structure of the packaged IMIC model file Figure 5 Data structure of the module's IMIC model file

6 detailed model description

6.1 Description rules 6.1.1 Features The description of the model file characteristics is not case sensitive, for example, 'M' and 'm' are treated as the same character. Recommend all in uppercase or All are in lowercase. 6.1.2 Available characters 6.1.2.1 Available characters A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, 1, 2, 3, 4,5,6,7,8,9,0, ,-,/, 6.1.3.3 Type 2 The detailed description should be placed on the next line of the keyword line, with no keywords ending the line. E.g. [TERMINAL] SUBCKTALVCH16244SIG1SIG2SIG3SIG4SIG5SIG6SIG7REFG 6.1.3.4 Type 3 The detailed description should be placed after [keyword] and there is no keyword to end the line in the same line. E.g. [NAME]ALVCH16244 6.1.4 Numbers and values 6.1.4.1 Overview The decimal point is represented by "." (the end point or period in the line) instead of the comma ",", which is in accordance with 6.6.8.1 part 2 of the ISO /IEC Directive. 20041) The purpose of calculation and processing is different. 1) ISO /IEC Directives, Part 2,.2004. Structure and Cartographic Rules in International Standards Scale factors for scientific notation are allowed, and scale factors or exponential expressions can be used. 6.1.4.2 Scale factor T(tera). 1012 G(giga). 109 MEG, X(mega). 106 K(kilo). 103 M (mili). 10-3 U (micro). 10-6 N (nano). 10-9 P (pico). 10-12 F(femto). 10-15 6.1.4.3 Scientific counting method Scientific counting should use "E". 6.1.4.4 Example 1.3X=1.3E6=1300K=1300E3=1300000 0.5U=5E-7=500N=500E-9=0.0000005 6.1.5 Notes When the first letter in a line is "*", the rest of the text in the line is a comment. When "$" appears anywhere in a row When set, the rest of the text in the line is a comment. 6.1.6 Continued Any statement starting with " " is a continuation of the previous statement. 6.1.7 Reserved word name The reserved words for the ideal ground reference are 0, GND, GND, and GROUND, so these reserved words cannot be used as signal names. 6.1.8 Description order The description of the file should follow the order of Figure 3, Figure 4 and Figure 5. The entries at the top of the vertical solid line should be described first, and the entry at the bottom is the last. Description, entries along the horizontal direction can appear in any order. 6.2 IC model file 6.2.1 File name 6.2.1.1 Overview The model file name begins with a letter or number and is suffixed with .IMC. 6.2.1.2 Example ALVCH16244.IMC Note. The limitation of the file name length (number of characters) depends on the operating system. 6.2.2 Start and end of model description 6.2.2.1 Overview The description of a model should represent a single IC model. 6.2.2.1.1 Description [IC] 6.2.2.1.2 Interpretation The model content follows the model description. 6.2.2.2 End of IC model description 6.2.2.2.1 Description [END_IC] 6.2.2.2.2 Interpretation The IC model description should end with this keyword. 6.2.3 Header files 6.2.3.1 Overview The IC type, model level, etc. should be described as the starting statement of the IC model. 6.2.3.2 IC type 6.2.3.2.1 Description [NAME] any text. 6.2.3.2.2 Interpretation Indicate the IC type identifier, including the product number or name. It is convenient for the simulator to select the correct model for the IC. 6.2.3.2.3 Example [NAME]ALVCH16244 6.2.3.3 Model version 6.2.3.3.1 Description [IMIC_VER] Any text. 6.2.3.3.2 Interpretation The version number of the IMIC specification should be described, and only version 1.3 is currently available. For IC models, the interpreter should follow the appropriate syntax rule. 6.2.3.3.3 Example [IMIC_VER]1.3 6.2.3.4 Model level 6.2.3.4.1 Description [LEVEL] integer 6.2.3.4.2 Interpretation Level 1. SI (Signal Integrity) Signal Noise Analysis Model. Level 2. PI (Power Integrity) A power supply noise analysis model including signal noise. Level 3. EMI (electromagnetic interference) electromagnetic radiation noise analysis model. This model is not available in this release. The detailed explanation is explained in Chapter 7. 6.2.3.4.3 Example [LEVEL]2 6.2.3.5 Date 6.2.3.5.1 Description [DATE]date 6.2.3.5.2 Interpretation The model release date can be described in any of the following formats. – day/month/year, for example. 23MAR98 – Month, year, for example. MARCH23,.1998 6.2.3.5.3 Example [DATE]23MAR98 6.2.3.6 Model interpretation 6.2.3.6.1 Description [NOTES] Any comments on the model should be described as needed, which may be used to explain the source, usage, and testing of the model. 6.2.3.6.2 Interpretation The following lines of [NOTES] can be used to describe any comments. 6.2.3.6.3 Example [NOTES] ELECTRICALMODELFORALVCH16244 6.2.3.7 Copyright 6.2.3.7.1 Description [COPYRIGHT]any text 6.2.3.7.2 Interpretation 6.2.3.7.3 Example [COPYRIGHT]COPYRIGHT1998,ZYXCORP.,ALLRIGHTSRESERVED 6.2.3.8 Manufacturer 6.2.3.8.1 Description [MANUFACTURER] arbitrary text 6.2.3.8.2 Interpretation The manufacturer declares here. 6.2.3.8.3 Example [MANUFACTURER]ZYXCORP. 6.2.4 Port 6.2.4.1 Overview The IC external port should be defined, and the external port is equivalent to the IC external pin. 6.2.4.2 Description [TERMINAL]any text 6.2.4.3 Explanation Define the external port of the IC. The data starts on the next line of [TERMINAL]. The external port signal name of [PAD_ASSIGNMENT] should be described. The IC type name follows the string ".SUBCKT" followed by the port name. 6.2.4.4 Example [TERMINAL] .SUBCKTALVCH16244SIG1SIG2SIG3SIG4SIG5SIG6SIG7REFG 6.2.5 Pad Assignment (See Figure 6) 6.2.5.1 Overview The interconnection between the die pad and the internal port of the package should be described. 6.2.5.2 Description [PAD_ASSIGNMENT]any text 6.2.5.3 Interpretation 6.2.5.4 Overview Describe the interconnection between the die pad and the internal port of the package. The data begins on the next line of [PAD_ASSIGNMENT]. The signal name of the internal port of the package connected to the chip pad should be the same as the corresponding chip declared by ".SUBCKT" in [CONNECTION] The signal names of the pads are the same. The data is given with the subcircuit instance declaration and begins with an "X". The subcircuit name of the top-level ".SUBCKT" in [CONNECTION] should appear after the port name at the end of the declaration. According to the SPICE tradition, common special reserved words (ie, signal names) used in chip instances and package instances mean that these ports are connected. Together. Note. If the die pad is not connected to any package pad, this die pad port should be connected to the signal "NO_CON- NECTION". If the internal port of the package is not connected to any chip pad, this internal port should be connected to the signal "NO_CON- NECTION". 6.2.5.5 Example In the following example, the chip's first port signal "SIG1I" is connected to the first port of the package. [PAD_ASSIGNMENT] XCHIP SIG1I SIG2I SIG3I SIG4I SIG5I SIG6I CHIP XPACKAGE SIG1I SIG2I SIG3I SIG4I SIG5I SIG6I SIG1 SIG2 SIG3 SIG4 SIG5 SIG6 SIG7 REFG PACKAGE [CONNECTION] SUBCKT CHIP PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 ENDSCHIP \u003cPackagemodelfile\u003e [CONNECTION] SUBCKT PACKAGE L1I L2I L3I L4I L5I L6I LEAD1 LEAD2 LEAD3 LEAD4 LEAD5 LEAD6 LEAD7 REFG ENDS PACKAGE Figure 6 Pad Assignment 6.2.6 Circuit description (see Figure 7 for example) 6.2.6.1 Overview The internal circuit components and their interconnections should be described. 6.2.6.2 Description [CONNECTION] [FAST] [TYP] [SLOW] [END_CONNECTION] 6.2.6.3 Interpretation 6.2.6.3.1 Overview The internal circuit components and their interconnections should be described, and the description ends with [END_CONNECTION]. [CONNECTION] is followed by a circuit description with a keyword. The following keywords are optional. [FAST] The fastest speed circuit description. [TYP] Typical speed circuit description. [SLOW] Minimum speed circuit description. The chip's internal circuitry contains a pad capacitance model declaration. The top level description of the internal circuit should be between ".SUBCKT" and ".ENDS". “.SUBCKT” should be described along with the subcircuit name and pad signal name of the top-level circuit. ".ENDS" should be described along with the subcircuit name of the top-level circuit. The circuit description is as follows. Element_Name \u003cNode_Name\u003e [Value][Model_Name]< [Parameter=Parameter_Value]> < > means repeatable, [] means optional. Optional components include. resistors, capacitors, inductors, mutual inductance, diodes, MOS transistors, diodes, voltage-controlled voltage sources, current-controlled current sources, voltage Control current source, flow control voltage source, lossless transmission line, independent voltage source, independent current source, sub circuit call, sub circuit description. Every component sound The first character of the description indicates the component type. The model name should be defined in the device description. Each component is described below. 6.2.6.3.2 Resistance Rxxxxxxxnode1node2valueormodel_name The unit is ohm. 6.2.6.3.3 Capacitance Cxxxxxxxnode1node2valueormodel_name The unit is Farah (F). 6.2.6.3.4 Self-inductance Lxxxxxxxnode1node2value 6.2.6.3.5 Mutual inductance Kxxxxxxxlname1lname2Coupling_coefficient Lname1 and lname2 are self-reported names. 6.2.6.3.6 Diode Dxxxxxxxnode1node2model_nameAREA=area_factor 6.2.6.3.7 MOS transistor Mxxxxxxxnode1node2node3node4model_name L=gate_lengthW=gate_width [ AD=drain_diffusion_area AS=source_diffusion_area] [ PD=perimeter_of_drain_junction PS=perimeter_of_source_junction] [ NRD=number_of_squares_of_drain_diffusion] [ NRS=number_of_squares_of_source_diffusion] The unit of gate length, gate width, perimeter of the drain node, perimeter of the source node, etc. is meters (m), and the area of the drain diffusion area and the source diffusion area are squared. Meter (m2). AD, AS, PD, PS, NRD, and NRS are optional. The default value is 0. These values do not have to match the true value of the chip size. The characteristics of individual transistors will be based on parameters such as L, W, AD, AS, PD, and PS. The resulting equation is calculated and defined in the device model description. See 6.2.8.3.3 for a detailed description. 6.2.6.3.8 Diode Qxxxxxxxnode1node2node3model_nameAREA=area_factor 6.2.6.3.9 Voltage-controlled voltage source Exxxxxxxnode1node2POLY=n \u003ccnode1cnode2\u003e\u003ck\u003e Cnode1 and cnode2 are control nodes, and k is a list of polynomial coefficients. 6.2.6.3.10 Flow Control Current Source Fxxxxxxxnode1node2POLY=n \u003cvname\u003e\u003ck\u003e Vname is the current source and k is the list of polynomial coefficients. 6.2.6.3.11 Voltage Control Current Source Gxxxxxxxnode1node2POLY=n \u003ccnode1cnode2\u003e\u003ck\u003e Cnode1 and cnode2 are control nodes, and k is a list of polynomial coefficients. 6.2.6.3.12 Flow Control Voltage Source Hxxxxxxxnode1node2POLY=n \u003cvname\u003e\u003ck\u003e Vname is the current source and k is the list of polynomial coefficients. 6.2.6.3.13 Lossless transmission line Txxxxxxxnode1node2node3node4Z0=characteristic_impedanceTD=transmission_delay 6.2.6.3.14 Independent voltage source 6.2.6.3.14.1 Overview Vxxxxxxxnode1node2[tranfun][DC=]dcvalue[AC=acmag,[acphase]] Dcvalue is the value of the DC voltage source, acmag is the amplitude of the AC voltage, acphase is the phase of the AC voltage, and tranfun is the transient A description of the function of the voltage source. 6.2.6.3.14.2 Pulse source function PULSEv1 v2[td [tr [tf [pw[per]]]]] Here v1 is the initial value, v2 is the pulse high value, td is the delay time, tr is the duration of the rising slope, and tf is the falling slope. Duration, pw is the pulse width and per is the pulse repetition period. 6.2.6.3.14.3 Sine source function SINvo va [freq [td [θ [φ]]]] Vo is the bias of voltage or current, va is the magnitude of voltage or current, freq is the frequency of voltage or current, td is the delay time, θ is Damping coefficient, φ is the phase delay time. 6.2.6.3.14.4 Exponential source function EXPv1 v2 [td [τ1 [td2 [τ2]]]] V1 is the initial value of voltage or current, v2 is the pulse value of voltage or current, td is the rising delay time, and td2 is the falling delay time. Τ1 is the rise time constant and τ2 is the fall time constant. 6.2.6.3.14.5 Piecewise linear source function PWLt1 v1 [t2 v2 t3 v3 ..][R[=repeat]][TD=delay] Vn(n=1,2,) is the voltage or current value, tn(n=1,2,) is the segmentation time, and repeat is the start time of the waveform. Repeated, delay is the delay time, and R causes the function to repeat. 6.2.6.3.14.6 Single frequency FM source function SFFMvo va [fc [mdi [fs]]] Vo is the voltage or current offset value, va is the magnitude of the voltage or current, fc is the carrier frequency, mdi is the modulation index value, and fs is a single frequency. 6.2.6.3.15 Independent current source Ixxxxxxxnode1node2[tranfun][DC=]dcvalue[AC=acmag,[acphase]] Dcvalue is the DC current source, acmag is the amplitude of the AC current, acphase is the phase of the AC current, tranfun is A functional description of the transient current source described in 6.2.6.3.14. 6.2.6.3.16 Subcircuit call Xxxxxxxx \u003cnode\u003e Subcircuit_name 6.2.6.3.17 Subcircuit definition .SUBCKTsubcircuit_name \u003cnode\u003e 6.2.6.4 Example Figure 7 Circuit Description Example Note. The ground signal of the IC internal circuit is connected to the ground port of the package. 6.2.7 Input excitation (see Figure 8) 6.2.7.1 Overview To describe the effect of the load on the output waveform of the buffer circuit, the input stimulus will be compared to the rising and falling edges of the output buffer circuit. Line definition. Figure 8 Input excitation 6.2.7.2 Input incentive allocation 6.2.7.2.1 Description [STIMULUS_ASSIGNMENT] External port name of [TERMINAL]IC [RISING] [FALLING] [END_STIMULUS_ASSIGNMENT] 6.2.7.2.2 Interpretation Define the input stimulus name of the output buffer circuit and control the output waveform of the IC. Input is exciting.

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