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GB/T 15879.604-2023: Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)
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Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)
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GB/T 15879.604-2023
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Basic data | Standard ID | GB/T 15879.604-2023 (GB/T15879.604-2023) | | Description (Translated English) | Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA) | | Sector / Industry | National Standard (Recommended) | | Classification of Chinese Standard | L55 | | Classification of International Standard | 31.200 | | Word Count Estimation | 18,167 | | Date of Issue | 2023-05-23 | | Date of Implementation | 2023-09-01 | | Issuing agency(ies) | State Administration for Market Regulation, China National Standardization Administration | GB/T 15879.604-2023: Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)
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ICS 31:200
CCSL55
National Standards of People's Republic of China
Mechanical standardization of semiconductor devices
Part 6-4: Surface mount semiconductor device packaging
General Rules for Outline Drawings Ball Array (BGA)
Package Dimensional Measurement Method
(IEC 60191-6-4:2003, IDT)
2023-05-23 release 2023-09-01 implementation
State Administration for Market Regulation
Released by the National Standardization Management Committee
foreword
This document is in accordance with the provisions of GB/T 1:1-2020 "Guidelines for Standardization Work Part 1: Structure and Drafting Rules for Standardization Documents"
drafting:
This document is Part 6-4 of GB/T 15879 "Mechanical Standardization of Semiconductor Devices": GB/T 15879 has been issued with
Lower part:
--- Part 4: Classification and coding system of semiconductor device package appearance;
--- Part 5: Recommended values for integrated circuit tape automatic bonding (TAB);
--- Part 6-4: Dimensions of general rules for drawing surface-mounted semiconductor device package outline drawings for ball array (BGA) packages
Measurement methods:
This document is equivalent to IEC 60191-6-4:2003 "Mechanical Standardization of Semiconductor Devices - Part 6-4: Surface Mount Semiconductor Devices
General Rules for Drawing Component Package Outline Drawings Dimensional Measurement Methods for Ball Array (BGA) Packages:
Please note that some contents of this document may refer to patents: The issuing agency of this document assumes no responsibility for identifying patents:
This document is proposed by the Ministry of Industry and Information Technology of the People's Republic of China:
This document is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78):
This document was drafted by: China Institute of Electronics Standardization, Ruijie Micro Technology (Zhengzhou) Co:, Ltd:, Shenzhen Smart Semiconductor
Co:, Ltd:, Aoshikang Precision Circuit (Huizhou) Co:, Ltd:
The main drafters of this document: An Qi, Li Kun, Fang Jiaen, Zhang Luhua, He Gaoqiang:
Introduction
GB/T 15879 "Mechanical Standardization of Semiconductor Devices" is proposed to be composed of 28 parts, corresponding to the conversion of IEC 60191 series standards
Standards, mainly including dimension symbols and definitions for semiconductor device outline drawing, drawing drawing rules, package outline classification and coding system, and
Standard outline drawings and recommended size ranges of standard packages for various semiconductor devices:
--- Part 1: Semiconductor outline drawing: The purpose is to specify the dimension symbols and definitions for drawing the outline drawing of semiconductor devices, drawing
rules and examples etc:
--- Part 2: Dimensions: The purpose is to specify the external dimension requirements of various semiconductor device packaging products:
--- Part 3: General principles for drawing outline drawings of integrated circuits: The purpose is to specify the dimension symbol code and
Definition, drawing rules and examples, etc:
--- Part 4: Classification and coding system of semiconductor device package appearance: The purpose is to specify the classification of semiconductor device package outline
Class and model nomenclature and coding system:
--- Part 5: Recommended values for integrated circuit tape automatic bonding (TAB): The purpose is to specify the automatic soldering of integrated circuit tape
recommended package size for the product:
--- Part 6: General rules for drawing surface mount semiconductor device package outline drawings: The purpose is to specify the surface mount semiconductor
General requirements and rules for drawing device package outline drawings:
--- Part 6-1: General rules for drawing surface mount semiconductor device package outline drawing Wing lead design guidelines: The purpose is
Standard outline drawings, dimensions and recommended range values for specified wing leads:
--- Part 6-2: General rules for drawing surface mount semiconductor device package outline drawings 1:50mm, 1:27mm, 1:00mm sections
Ball and Pillar Array Package Design Guidelines for pitch: The purpose is to specify 1:50mm, 1:27mm, 1:00mm pitch solder balls
Standard outline drawings, dimensions and recommended range values for and post array packages:
--- Part 6-3: General rules for drawing surface mount semiconductor device package outline drawings Dimensions of quad flat package (QFP)
Measurement methods: The purpose is to specify the measurement method of the quad flat package (QFP) external dimensions:
--- Part 6-4: Dimensions of general rules for drawing surface-mounted semiconductor device package outline drawings for ball array (BGA) packages
Measurement methods: The purpose is to specify the measurement method for the outline dimensions of ball array (BGA) packages:
--- Part 6-5: General rules for drawing surface mount semiconductor device package outline drawings Fine-pitch ball array package
(FBGA) size measurement method: The purpose is to specify the measurement method for the outline dimensions of fine-pitch ball array package (FBGA):
--- Part 6-6: General rules for drawing surface mount semiconductor device package outline drawings Fine-pitch land array package
(FLGA) size measurement method: The purpose is to specify the measurement of the outer dimensions of the fine-pitch land array package (FLGA)
method:
--- Part 6-7: General rules for dimensions of plastic very thin outline quad flat package (P-VQFN): The purpose is to stipulate the plastic
Standard dimensions and recommended range values for very thin outline quad flat package (P-VQFN):
--- Part 6-8: General rules for drawing surface mount semiconductor device package outline drawings Glass-sealed ceramic quad flat package
(G-QFP) Design Guidelines: The purpose is to specify the standard outline drawing and dimensions of glass-sealed ceramic quad flat package (G-QFP):
size and recommended range:
--- Part 6-9: General rules for drawing surface mount semiconductor device package outline drawings Plastic quad flat package (P-QFP)
Design Guidelines for Integrated Circuits: The purpose is to specify the standard outline drawing, dimensions of plastic quad flat package (P-QFP) integrated circuits
size and recommended range:
--- Part 6-10: General rules for drawing outline drawings of surface mount semiconductor device packages Plastic very thin small outline leadless packages
(P-VSON) size: The purpose is to specify the standard outline drawing, dimension
size and recommended range:
--- Part 6-11: Design guidelines for rectangular fine-pitch ball array packages (FBGA): The purpose is to specify the rectangular fine pitch solder ball
Standard outline drawings, dimensions and recommended range values for package in array (FBGA):
--- Part 6-12: General rules for drawing surface mount semiconductor device package outline drawings Fine-pitch land array package
(FLGA) Design Guidelines: The purpose is to specify the standard outline drawing, dimensions and promotion of fine-pitch land array package (FLGA):
recommended range:
--- Part 6-13: Close pitch ball array package (FBGA) and close pitch land array package (FLGA) top open fixture
design guidelines: The purpose is to specify the top of the fine pitch ball array package (FBGA) and the fine pitch land array package (FLGA)
Standard outline drawings, dimensions and recommended range values for open top grips:
--- Part 6-14: General rules for drawing surface mount semiconductor device package outline drawings Small outline J-lead package (SOJ)
method of size measurement: The purpose is to specify the method of measuring the external dimensions of small outline J-lead packages (SOJ):
--- Part 6-15: General rules for drawing surface mount semiconductor device package outline drawings Small outline package (SOP) Dimensional measurement
Quantitative method: The purpose is to specify the dimensional measurement method of Small Outline Package (SOP):
--- Part 6-16: Ball Array Package (BGA), Land Array Package (LGA), Fine Pitch Ball Array Package (FBGA) and dense
Glossary of pitch land array package (FLGA), semiconductor test and burn-in fixtures: The purpose is to specify the ball array package
(BGA), Land Array Package (LGA), Fine Pitch Ball Array Package (FBGA) and Fine Pitch Land Array Package
(FLGA), Definition of Semiconductor Test and Burn-in Fixtures:
--- Part 6-17: Stacked Package Design Guidelines for Fine Pitch Ball Array Package (FBGA) and Fine Pitch Land Array Package (FL-
GA): The purpose is to specify the standard outline of the fine-pitch ball array package (FBGA) and the fine-pitch land array package (FLGA):
Graphics, dimensions and recommended range values:
--- Part 6-18: General rules for drawing surface mount semiconductor device package outline drawings Design of ball array (BGA) packages
guide: The purpose is to specify standard outline drawings, dimensions and recommended range values for Ball Array (BGA) packages:
--- Part 6-19: Measurement method for high temperature package warpage and maximum allowable warpage: The purpose is to specify high temperature package warpage and maximum
A dimensional measurement method that allows for warpage:
--- Part 6-20: General rules for drawing surface mount semiconductor device package outline drawings J-lead small outline package (SOJ)
method of size measurement: The purpose is to specify the dimensional measurement method of J-lead Small Outline Package (SOJ):
--- Part 6-21: General rules for drawing surface mount semiconductor device package outline drawings Small outline package (SOP) Dimensional measurement
Quantitative method: The purpose is to specify the dimensional measurement method of Small Outline Package (SOP):
--- Part 6-22: General rules for drawing surface mount semiconductor device package outline drawings Silicon dense pitch ball array package
(S-FBGA) and Silicon Fine Pitch Land Array Package (S-FLGA) Design Guidelines: The purpose is to specify the silicon dense pitch solder ball array
Standard outline drawing, dimensions and recommended range values for column package (S-FBGA) and silicon fine pitch land array package (S-FLGA):
Mechanical standardization of semiconductor devices
Part 6-4: Surface mount semiconductor device packaging
General Rules for Outline Drawings Ball Array (BGA)
Package Dimensional Measurement Method
1 Scope
This document specifies the dimensional measurement method for Ball Array (BGA) packages:
The measurement methods specified in this document provide users with dimensional guarantees under the following agreed conditions:
a) The measurement is generally carried out manually or automatically;
b) If a dimension is not easily measurable directly, the best alternative measurement method will be determined as the preferred method:
2 Normative references
The contents of the following documents constitute the essential provisions of this document through normative references in the text: Among them, dated references
For documents, only the version corresponding to the date is applicable to this document; for undated reference documents, the latest version (including all amendments) is applicable to
this document:
IEC 60191-6:2009 Semiconductor device mechanical standardization Part 6: Surface mount semiconductor device package outline drawing
Note: IEC 60191-6:1990 referenced by IEC 60191-6-4:2003 has been replaced by IEC 60191-6:2009: Terms defined by IEC 60191-6:2009
and definitions still apply to this document (see Chapter 3):
3 Terms and Definitions
The terms and definitions defined in IEC 60191-6:2009 apply to this document:
4 Reference features and outline drawings
4:1 BGA outline drawing based on solder balls (first category)
See Figure 1 for a BGA outline drawing based on solder balls:
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