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Verification Regulation of General Digital Integrated Circuit Testing System
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JJG 1015-2006
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General Norm for Pattern Evaluation and Pattern Approval of Measuring Instruments
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Basic data Standard ID | JJG 1015-2006 (JJG1015-2006) | Description (Translated English) | Verification Regulation of General Digital Integrated Circuit Testing System | Sector / Industry | Metrology & Measurement Industry Standard | Classification of Chinese Standard | A56 | Classification of International Standard | 17.220 | Word Count Estimation | 18,183 | Date of Issue | 2006-12-08 | Date of Implementation | 2007-03-08 | Quoted Standard | AQSIQ Announcement No. 187 of 2006 | Regulation (derived from) | AQSIQ Announcement No. 187 2006 | Issuing agency(ies) | General Administration of Quality Supervision, Inspection and Quarantine | Summary | This standard applies to digital IC test systems, including hybrid integrated circuits and memory test system digital part of the initial verification, testing and use of follow-up inspection. |
JJG 1015-2006: Verification Regulation of General Digital Integrated Circuit Testing System---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Verification Regulation of General Digital Integrated Circuit Testing System
National Metrology Verification Regulations of the People's Republic
Universal digital integrated circuit test system
Released on.2006-12-08
2007-03-08 implementation
The General Administration of Quality Supervision, Inspection and Quarantine issued
Universal digital integrated circuit test system
Verification procedure
Stem
This regulation was approved by the General Administration of Quality Supervision, Inspection and Quarantine on December 8,.2006, and
Implemented on March 8,.2007.
Focal Point. National Radio Measurement Technology Committee
Drafting unit. Institute of Electronics Industry Standardization, Ministry of Information Industry
This procedure entrusts the National Radiometric Technical Committee to explain
The main drafters of this procedure.
Chen Dawei (Institute of Electronics Industry Standardization, Ministry of Information Industry)
Wu Jingyan (Institute of Electronics Industry Standardization, Ministry of Information Industry)
Participate in the drafters.
Zhou Xu (Institute of Electronics Industry Standardization, Ministry of Information Industry)
Wang Wei (Institute of Electronics Industry Standardization, Ministry of Information Industry)
table of Contents
1 Scope (1)
2 References (1)
3 Overview (1)
4 Metrology performance requirements (1)
4.1 Device Power (1)
4.2 Precision Measurement Unit (2)
4.3 drive unit (2)
4.4 Comparison unit (2)
4.5 System Clock (2)
5 General technical requirements (2)
6 measuring instrument control (2)
6.1 Verification conditions (2)
6.2 Verification items and verification methods (3)
6.3 Processing of verification results (10)
6.4 Verification cycle (10)
Appendix A Format of the Digital Integrated Circuit Test System Verification Certificate and Verification Result Notice (11)
General digital integrated circuit test system verification procedures
1 Scope
This procedure applies to digital integrated circuit test systems, including numbers for hybrid integrated circuits and memory test systems.
Part of the first verification, subsequent verification and in-use inspection.
2 reference files
JJF1059-1999 "Measurement and Expression of Measurement Uncertainty"
Note. When using this procedure, care should be taken to use the current valid version of the above cited documents.
3 Overview
The general purpose digital integrated circuit test system test object is a digital logic integrated circuit device. Can be used for wafer measurement
Test and product testing, product inspection, analysis, screening and other tests after packaging. Typical structure consists of a drive/compare unit,
Graphic generator, clock generator, precision measurement unit, device power supply and control unit. Hybrid circuit test system
The digital test unit in the system and the memory test system is basically the same as the digital integrated circuit test system. For it
Their digital test unit verification is equivalent to a general purpose digital integrated circuit test system. The following is a digital signal test system
Schematic.
Figure 1 Schematic diagram of the integrated circuit test system
This procedure is the main unit of the digital integrated circuit test system through the sub-parameter verification and standard swatch measurement.
Performance parameters are calibrated to ensure traceability of critical values of the test system.
4 Metrological performance requirements
4.1 Device Power Supply
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