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GB/T 7611-2016 English PDF

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GB/T 7611-2016: Characteristics of the electrical interface at hierarchical bit rate for digital network
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GB/T 7611: Evolution and historical versions

Standard IDContents [version]USDSTEP2[PDF] delivered inStandard Title (Description)StatusPDF
GB/T 7611-2016English1999 Add to Cart 13 days [Need to translate] Characteristics of the electrical interface at hierarchical bit rate for digital network Valid GB/T 7611-2016
GB/T 7611-2001EnglishRFQ ASK 3 days [Need to translate] Characteristics of the electrical interface at hierarchical bit rate for digital network Obsolete GB/T 7611-2001
GB/T 7611-1987EnglishRFQ ASK 3 days [Need to translate] Parameters of digital interface for PCM systems over telecommunication network Obsolete GB/T 7611-1987

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Basic data

Standard ID GB/T 7611-2016 (GB/T7611-2016)
Description (Translated English) Characteristics of the electrical interface at hierarchical bit rate for digital network
Sector / Industry National Standard (Recommended)
Classification of Chinese Standard M19
Classification of International Standard 33.040.50
Word Count Estimation 100,156
Date of Issue 2016-04-25
Date of Implementation 2016-12-01
Older Standard (superseded by this standard) GB/T 7611-2001
Regulation (derived from) National Standard Announcement No
Issuing agency(ies) General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China, Standardization Administration of the People's Republic of China

GB/T 7611-2016: Characteristics of the electrical interface at hierarchical bit rate for digital network


---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Characteristics of the electrical interface at hierarchicalbit rate for digital network ICS 33.040.20 M19 National Standards of People's Republic of China Replace GB/T 7611-2001 Digital network series bit rate electrical interface characteristics 2016-04-25 released 2016-12-01 implementation General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China China National Standardization Management Committee released Directory Preface Ⅸ 1 Scope 1 2 normative reference document 1 3 Terms and definitions 2 4 acronym 3 5 Electrical interface physical/electrical characteristics 4 5.1 64kbit/s interface 4 5.1.1 Basic requirements 4 5.1.1.1 Interface Type 4 5.1.1.2 basic functional requirements of the interface 4 5.1.1.3 Interface Rate and Tolerance 5 5.1.1.3.1 Co-directional Interface Rate and Tolerance 5 5.1.1.3.2 Centralized Interface Rate and Tolerance 5 5.1.1.3.3 Reverse Interface Rate and Tolerance 5 5.1.1.4 Interface configuration and code conversion 5 5.1.1.4.1 co-directional interface configuration and code conversion 5 5.1.1.4.2 Centralized interface configuration and code conversion 6 5.1.1.4.3 Reverse interface configuration and code conversion 7 5.1.1.5 Overvoltage protection of interface 8 5.1.1.5.1 Over-voltage protection for co-directional interface 8 5.1.1.5.2 Overvoltage protection for centralized interface 8 5.1.1.5.3 Reverse interface overvoltage protection 8 5.1.2 Output requirements 8 5.1.2.1 Output impedance and load impedance 8 5.1.2.1.1 Output impedance and load impedance of the interface 5.1.2.1.2 Reverse Interface Output Impedance and Load Impedance 9 5.1.2.2 Output waveform and parameter 9 5.1.2.2.1 Output waveform and parameter 9 for synchronous interface 5.1.2.2.2 Centralized interface output waveform and parameter 10 5.1.2.2.3 Reverse interface output waveform and parameter 11 5.1.3 Input Requirements 12 5.1.3.1 Centralized input port characteristics 12 5.1.3.2 Input impedance of the same type of interface 13 5.1.3.3 Reverse Interface Input Impedance 13 5.1.3.4 Receiver sensitivity for the same type of interface 13 5.1.3.5 Reverse interface reception sensitivity 13 5.1.3.6 Anti-jamming capability of the same type of interface input port 14 5.1.3.7 Reverse interface input port Anti-jamming capability 14 5.1.4 Outer conductor and shield ground 5.2 2048 kbit/s interface (E12) 14 5.2.1 Basic requirements 14 5.2.1.1 Rate and Tolerance 14 5.2.1.2 Interface Code 14 5.2.1.3 Overvoltage protection 14 5.2.2 Output requirements 14 5.2.2.1 Output port load impedance and output impedance 14 5.2.2.2 Output Output Signal Waveform and Related Parameters 15 5.2.3 Input Requirements 16 5.2.3.1 Input impedance characteristics 16 5.2.3.2 Input Sensitivity 17 5.2.3.3 Input port anti-interference ability 17 5.2.4 Outer conductor and shield ground 5.3 8448kbit/s interface (E22) 17 5.3.1 Basic requirements 17 5.3.1.1 Rate and Tolerance 17 5.3.1.2 Interface Code 17 5.3.1.3 Overvoltage protection 17 5.3.2 Output requirements 17 5.3.2.1 Output port impedance and output impedance 17 5.3.2.2 Output output signal waveform and related parameters 18 5.3.3 Input Requirements 19 5.3.3.1 Input port impedance 19 5.3.3.2 Input Sensitivity of Input Port 5.3.3.3 Input port anti-interference ability 20 5.3.4 Outer conductor and shield ground 5.4 34368 kbit/s interface (E31) 20 5.4.1 Basic requirements 20 5.4.1.1 Rate and Tolerance 20 5.4.1.2 Interface code 20 5.4.1.3 Overvoltage protection 20 5.4.2 Output requirements 20 5.4.2.1 Output port impedance and output impedance 20 5.4.2.2 Output signal waveform and related parameters 21 5.4.3 Input Requirements 22 5.4.3.1 Input port impedance 22 5.4.3.2 Input Receiving Sensitivity 22 5.4.3.3 Input port anti-interference ability 22 5.4.4 Outer conductor and shield ground 5.5 44736kbit/s interface 22 5.5.1 Basic requirements 22 5.5.1.1 Rate and Tolerance 22 5.5.1.2 Interface Code 22 5.5.1.3 Overvoltage protection 23 5.5.2 Physical characteristics requirements 23 5.6 139264 kbit/s interface (E4) 24 5.6.1 Basic requirements 5.6.1.1 Rate and Tolerance 24 5.6.1.2 Interface Code 25 5.6.1.3 Overvoltage protection 25 5.6.2 Output requirements 25 5.6.2.1 Output Output Impedance and Load Impedance 25 5.6.2.2 Output signal waveform and related parameters 25 5.6.3 Input Requirements 27 5.6.3.1 Input port impedance 27 5.6.3.2 Input Sensitivity 27 5.6.4 Outer conductor and shield ground 5.7 51840 kbit/s interface (STM-0 interface) 27 5.7.1 Basic requirements 27 5.7.1.1 Rate and Tolerance 27 5.7.1.2 Interface Code 27 5.7.1.3 Overvoltage protection 27 5.7.2 Output requirements 28 5.7.2.1 Output impedance and load impedance 28 5.7.2.2 Output waveforms and associated parameters 5.7.3 Input Requirements 28 5.7.3.1 Input impedance 28 5.7.3.2 Input Sensitivity 29 5.7.4 Specifications on cross-connect points 30 5.7.4.1 Signal power level 30 5.7.4.2 Eye view 30 5.7.5 External conductor and shield ground 5.8 155520 kbit/s interface (STM-1e) 31 5.8.1 Basic requirements 31 5.8.1.1 Rate and Tolerance 31 5.8.1.2 Interface Code 31 5.8.1.3 Overvoltage protection 31 5.8.2 Output requirements 31 5.8.2.1 Output impedance and load impedance 31 5.8.2.2 Output port waveform and related parameters 31 5.8.3 Input Requirements 33 5.8.3.1 Input impedance 33 5.8.3.2 Input Sensitivity 34 5.8.4 Specifications on cross-connect points 5.8.4.1 Signal power level 34 5.8.4.2 eye diagram 34 5.8.5 External conductor and shield ground 5.9 2048kHz Synchronous Timing Interface 5.9.1 Basic requirements 35 5.9.1.1 Frequency and Tolerance 35 5.9.1.2 Overvoltage protection capability 35 5.9.2 Output requirements 35 5.9.2.1 Output impedance and load impedance 35 5.9.2.2 Output waveforms and associated parameters 5.9.3 Input Requirements 37 5.9.3.1 Input impedance 37 5.9.3.2 Input Sensitivity 37 5.9.4 Outer conductor and shield ground 5.10 time synchronization interface 37 5.10.1 Time/phase allocation interface based on V.11 5.10.1.1 Overview 37 5.10.1.2 1PPS rising and falling edge requirements 5.10.1.3 Signal timing 39 5.10.2 1PPS phase synchronization test interface 40 5.10.2.1 Overview 40 5.10.2.2 Performance requirements 40 5.10.2.3 Voltage level 40

6 electrical interface frame structure requirements

6.1 2048kbit/s interface 40 6.1.1 Basic frame frame length 40 6.1.2 Arrangement of bits in basic frame 6.1.2.1 Arrangements for the first to eighth bits (TS0) in the basic frame 6.1.2.2 Arrangements for the 9th to the 256th bit in the frame 41 6.1.3 Frame frame loss and recovery criteria for this frame (algorithm) 43 6.1.3.1 Basic frame frame location loss decision criterion 43 6.1.3.2 Basic frame frame location recovery decision criterion 43 6.1.4 CRC multiframe positioning 43 is performed using the first bit information in the basic frame 6.1.4.1 Where applicable 43 6.1.4.2 CRC-4 multiframe structure 43 6.1.4.3 Arrangement of bits in CRC-4 multiframe 6.1.4.4 Interworking between CRC-4 function devices and devices that do not have CRC-4 functions 6.1.4.5 CRC-4 multiframe positioning algorithm 45 6.1.4.5.1 Overview 45 6.1.4.5.2 CRC-4 multiframe positioning basic algorithm 45 Improved algorithm for CRC-4 multiframe positioning 6.1.4.6 Termination Endpoint Processing (CRC-4 Start and End Endpoint Processing) 48 6.1.4.7 Intermediate processing of CRC-4 remainder 49 6.1.4.8 Use of CRC-4 detection/monitoring capabilities 49 6.1.4.8.1 Detection of Pseudo Framing Positioning 6.1.4.8.2 Bit error on-line monitoring 50 6.1.5 Synchronization state San bit 50 6.2 Frame structure of different bit rate bearer channels in 2048 kbit/s interface 6.2.1 Overview 52 6.2.2 Frame characteristics of 64 kbit/s channels 6.2.2.1 Basic requirements 52 6.2.2.2 Use of time slots TS1 to TS31 52 6.2.3 n × 64kbit/s interface (frame characteristics carrying n × 64 kbit/s channel) 52 6.2.3.1 Basic requirements 52 6.2.3.2 Use of time slots TS1 to TS31 52 6.2.4 Multiple n × 64 kbit/s interfaces (frame characteristics carrying one or more n × 64 kbit/s channels) 53 6.2.4.1 Basic requirements 53 6.2.4.2 Use of time slots TS1 to TS31 53 6.2.5 Common Channel Signaling 54 6.2.6 Multiframe and multiframe characteristics of road signaling 6.2.6.1 Basic requirements 54 6.2.6.2 Use of time slots TS1 to TS31 54 6.2.6.3 Road Signaling Multiframe Structure 6.2.6.4 Multiframe location loss and multiframe positioning recovery with track signaling multiframe 6.3 8448kbit/s interface 56 6.3.1 Basic frame structure 56 6.3.2 Arrangements for each bit within the frame 6.3.2.1 bits 1 to 8 bits in TS0 and 1 to 6 bits in TS66 - frame positioning bits 56 6.3.2.2 7, 8 bits 56 in TS66 6.3.2.3 Slot 1 to 8 bits in slot TS33 6.3.2.4 Slots 1 to 8 bits in slot TS99 --- For cyclic redundancy check -6 (CRC-6) 56 6.3.2.5 Basic time slot TS1 to time slot TS32, time slot TS34 to time slot TS65, time slot TS67 to time slot TS98, The time slot TS100 to the first to eighth bits 57 in slot 131 6.3.3 8448kbit/s basic frame location loss and recovery 6.4 8448kbit/s interface frame structure for different bit rate bearer channels 6.4.1 Overview 57 6.4.2 8448kbit/s interface frame structure for common channel signaling 6.4.2.1 Basic requirements 58 6.4.2.2 The use of bits within the frame 58 6.4.4 channel channel signaling 8448 kbit/s interface frame structure 58 6.4.3.1 Basic requirements 58 6.4.3.2 Application of Bits in Bits 58 6.4.3.3 with the road signaling multiframe 58 6.5 44736kbit/s interface 59 6.5.1 Multiple frame length 59 6.5.2 Multiframe overhead bits 59 6.5.3 Distribution of multiframe overhead bits 6.5.3.1 Overview 60 6.5.3.2 X bits (X1, X2) 60 6.5.3.3 P bits (P1, P2) 60 6.5.3.4 Multiframe positioning signals (M1, M2, M3) 60 6.5.3.5 M subframe positioning signals (F1, F2, F3, F4) 61 6.5.3.6 C bits (C11, C12, C13, C21, .. Cij, .., C73) 61 6.5.3.7 44736kbit/s Two specific models used 6.5.3.7.1 Overview 66 6.5.3.7.2 Alarm Indication Signal (AIS) 66 6.5.3.7.3 Idle signal (IDLE) 66 6.6 STM-0 and STM-1e interfaces 66

7 Electrical interface jitter and drift requirements

7.1 Network limit for service interface 66 7.1.1 Output jitter 66 7.1.2 Output drift 67 7.1.2.1 Overview 67 7.1.2.2 2048kbit/s interface output drift limit 68 7.1.2.3 34368kbit/s interface output drift limit 69 7.1.2.4 44736kbit/s interface output drift limit 69 7.1.2.5 139264kbit/s interface output drift limit 70 7.2 Network limit for synchronous interface 70 7.2.1 Overview 70 7.2.2 Output jitter 71 7.2.3 Output drift 71 7.2.3.1 Overview 71 7.2.3.2 PRC interface output drift limit 72 7.2.3.3 SSU interface output drift limit 72 7.2.3.4 SEC Interface Output Drift Limit 74 7.2.3.5 PDH Synchronization Interface Output Drift Limit 75 7.3 The input margin of the service interface 77 7.3.1 Overview 77 7.3.2 64 kbit/s input jitter and drift tolerance 78 7.3.3 2048kbit/s Input Jitter and Drift Tolerances 79 7.3.4 8448 kbit/s input jitter and drift tolerance 80 7.3.5 34368 kbit/s Input jitter and drift tolerance 81 7.3.6 44736kbit/s Input jitter and drift tolerance 82 7.3.7 139264kbit/s Input jitter and drift tolerance 83 7.3.8 155520kbit/s Input jitter and drift tolerance 84 7.4 Input margin for synchronous interface 85 Appendix A (normative) Regulations and tests for overvoltage protection requirements Appendix B (normative) HDB3 and B3ZS Code Encoding Rules Appendix C (Normative Appendix) CMI Code Encoding Rules 89 Appendix D (informative) Background information on CRC processing 90

Foreword

This standard is drafted in accordance with the rules given in GB/T 1.1-2009. This standard replaces GB/T 7611-2001 "digital network series bit rate electrical interface characteristics", this standard revision of all technical content according to The latest changes to the international standards have been updated and the contents of the scope of this standard have been removed. This standard is in line with GB/T 7611-2001 The main technical changes are as follows. - Amend the relevant requirements of Appendix 44 to the 44736kbit/s interface to 5.5 (see Appendix 5 of the.2005 edition); - Amend the relevant requirements of Appendix N to the STM-0 interface to 5.7 (see Appendix 7 of the .7.7,.2001 edition); - Increased frame structure requirements for STM-N based on the interface type specified in G.703 (see 6.6); - Deletion in Appendix C related to the abolished ITU-T Recommendation K.41 (Protection of the internal interface of the bureau to over-voltage protection) The relevant references in the general requirements of the interfaces in Chapters 5 through 11 are modified to refer to ITU-T Recommendation K.20 (see Chapter 5 - Chapter 11, Appendix C of the.2001 edition); - delete the contents of the test methods in Chapters 5 to 12 and Appendix E, Appendix F, Appendix G, Appendix H (see.2001 Edition 5 to Chapter 11 and Appendix E, Appendix F, Appendix G, Appendix H); --- delete 6.4.2 with 384kbit/s interface, 320kbit/s interface, V4 interface related content (see the.2001 version of 6.4.2); - Based on the requirements of G.703, modify the requirements for the 2048kHz output frequency offset in 11.1.1 (see 5.1.1,.2001, 11.1.1); - Deleting Appendix A, the requirements for bit tolerance have been specified in the basic requirements of each interface in Chapter 5 (see Appendix A of the.2001 edition); - Delete Appendix K, this standard does not specify the detection clearance threshold for LOS/AIS/RDI (see Appendix K of the.2001 edition); - Deleting appendix M, the requirements for impedance characteristics have been specified in the basic requirements of each interface in Chapter 5 (see Appendix M of the.2001 edition); This standard refers mainly to ITU-TG.703 "Physical/Electrical Characteristics of Digital Serial Interface", G.704 "1544, 6312, 2048, 8448, 44736kbit/s series of frame structures ", G.707" Synchronous Digital System (SDH) Network Node Interface ", G.823" to 2048kb/s Series-based digital network jitter and drift control ", G.825" SDH-based digital network jitter and drift control " Revised. Please note that some of the contents of this document may relate to patents and that the issuer of this document does not assume responsibility for the identification of these patents. This standard is proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This standard is owned by the Ministry of Industry and Information Technology (communications). The drafting unit of this standard. Ministry of Industry and Information Technology Telecommunications Research Institute. The main drafters of this standard. Wang Jianhua, Pan Feng, Hu Changjun, Zhang Haiyi, Xu Yijun, Du Sen, Wang Yanfang, Jichen. This standard replaced the previous version of the standard release. --- GB/T 7611-2001. Digital network series bit rate electrical interface characteristics

1 Scope

This standard specifies the electrical interface characteristics of the digital network series bit rate, including 64kbit/s, 2048kbit/s, 8448kbit/s, 34868 kbit/s, 44736 kbit/s, 139264 kbit/s, 51840 kbit/s (STM-0), 155520 kbit/s (STM-1e) Speed electrical interface, 2048kHz synchronous timing interface and time synchronization interface physical/electrical characteristics, 2048kbit/s basic frame, 2048kbit/s Different bit rate in the interface bearer channel, 8448kbit/s basic frame, 8448kbit/s interface in different bit rate bearer channel, 44736kbit/s interface, STM-0 and STM-1e interface and other electrical interface frame structure requirements, as well as a variety of PDH and SDH electrical interface Drift and jitter requirements. This standard applies to digital network based on electrical interface network planning, interoperability between networks, network maintenance operations, equipment maintenance and equipment acceptance.

2 normative reference documents

The following documents are indispensable for the application of this document. For dated references, only the dated edition applies to this article Pieces. For undated references, the latest edition (including all modifications) applies to this document. Technical requirements for SDH equipment - clocks Method of Transmitting Synchronous Network Timing in SDH Network The physical/electrical characteristics of the ITU-TG.703 digital serial interface (Physical/electricalcharacteristicsofhierarchical digitalinterfaces ITU-TG.706 Frame location and cyclic redundancy check (CRC) associated with the basic frame structure specified in G.704 (Framea- lignmentandcyclicredcheck (CRC) proceduresrelatingtobasicframestructuresdefinedin recommendationG.704) ITU-TG.707 synchronous digital system (SDH) network node interface (Networknodeinterfaceforthesynchronous digitalhierarchy (SDH) ITU-TG.752 based on the secondary group rate of 6312kbit/s and the use of positive decision of the characteristics of digital multiplexing equipment (Charac- teristicsofdigitalmultiplexequipmentsbasedonasecondorderbitrateof6312kbit/sandusingpos- itivejustification ITU-TG.761 60-channel code converter common features (Generalcharacteristicsofa60-channeltranscode equipment ITU-TG.811 timing characteristics of the reference clock (Timingcharacteristicofprimaryreferenceclocks) ITU-TG.812 applies to synchronous network node timing requirements from clock (Timingrequirementsofslaveclockssuitable foruseasnodeclocksinsynchronizationnetworks) ITU-TG.813 timing requirements for SDH device clock (SEC) (TimingcharacteristicsofSDHequipmentslave clocks (SEC)) ITU-TG.822 Controlled Slip Rate Indicators in International Digital Connectivity (Controledsliprateobjectivesonaninterna- tionaldigitalconnection ITU-TG.823 Control of digital network jitter and drift based on 2048kb/s series (Thecontrolofjitterand wanderwithindigitalnetworkswhicharebasedonthe2048kbit/shierachy) ITU-TG.825 Control of digital network jitter and drift based on SDH (Thecontrolofjitterandwander

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