|
US$484.00 ยท In stock
Delivery: <= 4 days. True-PDF full-copy in English will be manually translated and delivered via email.
GB/T 43034.2-2024: Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method
Status: Valid
| Standard ID | Contents [version] | USD | STEP2 | [PDF] delivered in | Standard Title (Description) | Status | PDF |
| GB/T 43034.2-2024 | English | 484 |
Add to Cart
|
4 days [Need to translate]
|
Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method
| Valid |
GB/T 43034.2-2024
|
PDF similar to GB/T 43034.2-2024
Basic data | Standard ID | GB/T 43034.2-2024 (GB/T43034.2-2024) | | Description (Translated English) | Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method | | Sector / Industry | National Standard (Recommended) | | Classification of Chinese Standard | L56 | | Classification of International Standard | 31.200 | | Word Count Estimation | 24,213 | | Date of Issue | 2024-10-26 | | Date of Implementation | 2024-10-26 | | Issuing agency(ies) | State Administration for Market Regulation, China National Standardization Administration | GB/T 43034.2-2024: Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method
---This is an excerpt. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.), auto-downloaded/delivered in 9 seconds, can be purchased online: https://www.ChineseStandard.net/PDF.aspx/GBT43034.2-2024
ICS 31.200
CCSL56
National Standard of the People's Republic of China
Integrated circuit pulse immunity measurement
Part 2.Synchronous transient injection method
(IEC TS62215-2.2007, IDT)
Released on October 26, 2024
Implementation on October 26, 2024
State Administration for Market Regulation
The National Standardization Administration issued
Table of Contents
Preface III
Introduction IV
1 Scope 1
2 Normative references 1
3 Terms and Definitions 1
4 General Provisions 2
4.1 Overview 2
4.2 Measurement Principle 2
4.3 Layout Principles 3
4.4 Response Signal 3
4.5 Coupling Network 3
4.6 Breadboard 7
4.7 Special requirements for IC 7
5 Test conditions 8
5.1 Default test conditions 8
5.2 Pulse immunity of the test arrangement 8
6 Test Arrangement 8
6.1 Overview 8
6.2 Test Equipment 9
6.3 Test arrangement description 9
6.4 Signal Relationship Description 10
6.5 Calculation of the number of measurements and time step 10
6.6 Test procedure 11
6.7 Monitoring and Inspection 11
6.8 System Confirmation 11
7 Test Report 11
7.1 General Principles 11
7.2 Immunity Limits or Levels 12
7.3 Performance Classification 12
7.4 Description and comparison of test results 12
Appendix A (Informative) Flowchart of the software used in the microcontroller 13
Appendix B (Informative) Flowchart of the test arrangement control software (bus control program) 14
Appendix C (Informative) Test Board Requirements 15
Reference 18
Preface
This document is in accordance with the provisions of GB/T 1.1-2020 "Guidelines for standardization work Part 1.Structure and drafting rules for standardization documents"
Drafting.
This document is Part 2 of GB/T 43034 "Measurement of pulse immunity of integrated circuits". GB/T 43034 has been published as follows
part.
--- Part 2.Synchronous transient injection method;
--- Part 3.Asynchronous transient injection method.
This document is equivalent to IEC TS62215-2.2007 "Integrated circuit pulse immunity measurement Part 2.Synchronous transient injection
The document type was adjusted from IEC technical specifications to my country's national standards.
Please note that some of the contents of this document may involve patents. The issuing organization of this document does not assume the responsibility for identifying patents.
This document is proposed by the Ministry of Industry and Information Technology of the People's Republic of China.
This document is under the jurisdiction of the National Technical Committee for Standardization of Integrated Circuits (SAC/TC599).
This document was drafted by. China Electronics Technology Standardization Institute, Shenzhen Beice Standard Technology Service Co., Ltd., Anhui Zhongren Beijia
Technology Co., Ltd., the Fifth Electronic Research Institute of the Ministry of Industry and Information Technology, Xiamen Hainoda Scientific Instrument Co., Ltd., Tianjin Advanced Technology Research Institute,
Beijing Zhixin Microelectronics Technology Co., Ltd., Suzhou Test Electronic Technology Co., Ltd., Nanjing Rongce Testing Technology Co., Ltd., Zhejiang Nuoyi
Technology Co., Ltd., Yangxin Technology (Shenzhen) Co., Ltd., National Radio Monitoring Center Testing Center, China Household Electrical Appliances Research Institute, China Information
Information Communication Research Institute, Nanjing Normal University, and Dongguan Vocational and Technical College.
The main drafters of this document are. Fu Jun, Cui Qiang, Fang Wenxiao, Wu Jianfei, Zhang Haifeng, Zhang Yanyan, Mo Guoyan, Li Yang, Liang Jiming, Hu Xiaojun,
Xing Liwen, Zheng Yimin, Yang Hongbo, Dong Qifeng, Xiong Yufei, Yan Wei, Chu Rui, Kang Zhineng, Wei Haihong, and Chen Meishuang.
introduction
To standardize the pulse immunity measurement of integrated circuits and provide pulse immunity measurement methods for integrated circuit manufacturers and testing institutions.
GB/T 43034 specifies the general conditions, definitions and test procedures for different injection measurement methods for integrated circuit pulse immunity measurements.
The test requirements are planned to consist of two parts.
--- Part 2.Synchronous transient injection method. The purpose is to specify the test procedures and test requirements of the synchronized transient injection method.
--- Part 3.Asynchronous transient injection method. The purpose is to specify the test procedures and test requirements for the asynchronous transient injection method.
Integrated circuit pulse immunity measurement
Part 2.Synchronous transient injection method
1 Scope
This document gives general information and definitions for the test methods used to evaluate the immunity of integrated circuits (ICs) to fast conducted synchronous transient disturbances.
This information includes test conditions, test equipment, test arrangement, test procedures and test report content requirements.
The purpose of this document is to describe the general conditions for obtaining quantitative measurements of IC immunity by establishing the same test environment.
Deviations from this document must be clearly noted in the test report.
The synchronous transient immunity test method given in this document is to use a fast rise time transient with different amplitude, duration and polarity.
The short pulse is coupled to the IC by conduction. In this method, the applied pulse needs to be synchronized with the functional operation of the IC to ensure controllable
and reproducible conditions.
2 Normative references
This document has no normative references.
3 Terms and Definitions
The following terms and definitions apply to this document.
3.1
Auxiliary equipment auxiliaryequipment;AE
The non-permitted devices necessary to establish full functionality and determine correct performance (operation) of the device under test (DUT) when exposed to disturbances.
Test equipment.
3.2
coupling network couplingnetwork
A circuit with specified impedance and known transfer characteristics used to transfer energy from one circuit to another.
3.3
Device under test; DUT
The device, equipment, or system being evaluated.
NOTE. In this document, DUT refers to the semiconductor device under test.
3.4
The equipment or system can work normally in its electromagnetic environment and does not cause any unacceptable electromagnetic disturbance to anything in the environment.
ability.
[Source. IEC 60050-161.1990, 161-01-07]
3.5
electrical noise
Unwanted electrical signals that can produce harmful effects in the circuits of a control system.
[Source. IEEE std 100-1992-518-1982]
|