GB/T 7497.1-2008 English PDF

US$774.00 · In stock
Delivery: <= 4 days. True-PDF full-copy in English will be manually translated and delivered via email.
GB/T 7497.1-2008: Microprocessor system bus. 8-bit and 16-bit data (MULTIBUS Ⅰ) -- Part 1: Functional description with electrical and timing specifications
Status: Valid

GB/T 7497.1: Historical versions

Standard ID	USD	BUY PDF	Lead-Days	Standard Title (Description)	Status
GB/T 7497.1-2008	774	Add to Cart	4 days	Microprocessor system bus. 8-bit and 16-bit data (MULTIBUS Ⅰ) -- Part 1: Functional description with electrical and timing specifications	Valid
GB/T 7497.1-1987	RFQ	ASK	9 days	Microprocessor system bus I, 8-bit and 16-bit data--Part 1: Functional description with electrical and timing specifications	Obsolete

Similar standards

GB/T 37720   SJ/T 11590   GB/T 29768   GB/T 18233.4   GB/T 34961.2   GB/T 7497.2   

Basic data

Standard ID: GB/T 7497.1-2008 (GB/T7497.1-2008)
Description (Translated English): Microprocessor system bus. 8-bit and 16-bit data (MULTIBUS ��) -- Part 1: Functional description with electrical and timing specifications
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: L65
Classification of International Standard: 35.200
Word Count Estimation: 39,344
Date of Issue: 2008-08-06
Date of Implementation: 2009-01-01
Older Standard (superseded by this standard): GB/T 7497.1-1987
Adopted Standard: IEC 60796-1-1990, IDT
Regulation (derived from): Announcement of Newly Approved National Standards No. 12 of 2008 (No. 125 overall)
Issuing agency(ies): General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China, Standardization Administration of the People's Republic of China
Summary: This standard applies to interconnect data processing, data storage and other peripheral control devices configured interface tightly coupled system components. The interface system has to allow the interaction of various system components necessary to signal that allows the memory and I/O data transfer, a direct memory access, and an interrupt is generated and so on. This standard form for all elements of the system bus to provide a detailed description and characteristics of both.

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