GB/T 42848-2023 English PDF

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GB/T 42848-2023: Semiconductor integrated circuits - Test method of direct digital frequency synthesizer
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Basic data

Standard ID: GB/T 42848-2023 (GB/T42848-2023)
Description (Translated English): Semiconductor integrated circuits - Test method of direct digital frequency synthesizer
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: L56
Classification of International Standard: 31.200
Word Count Estimation: 34,367
Date of Issue: 2023-08-06
Date of Implementation: 2023-12-01
Issuing agency(ies): State Administration for Market Regulation, China National Standardization Administration

GB/T 42848-2023: Semiconductor integrated circuits - Test method of direct digital frequency synthesizer

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
ICS 31.200 CCSL56 National Standards of People's Republic of China Semiconductor integrated circuit Direct digital frequency synthesizer test method Published on 2023-08-06 Implemented on 2023-12-01 State Administration for Market Regulation Released by the National Standardization Administration Committee

Table of contents

Preface III 1 Scope 1 2 Normative reference documents 1 3 Terms and Definitions 1 4 General Provisions 3 4.1 Test environment 3 4.2 Test Notes 3 4.3 Related documents 3 5 static parameters 3 5.1 Logic input high level voltage VIH 3 5.2 Logic input low level voltage VIL 4 5.3 Logic output high-level voltage VOH 5 5.4 Logic output low level voltage VOL 6 5.5 Logic input high level current IIH 7 5.6 Logic input low level current IIL 8 5.7 Gain error EG 8 5.8 Integral nonlinearity INL 10 5.9 Differential nonlinearity DNL 11 5.10 Full scale output current IFS 12 5.11 Output offset current IOO 13 5.12 Voltage adaptation range VDAC 13 5.13 Clock input bias voltage Vb 14 6 Dynamic Parameter Test 15 6.1 Setup time tSU 15 6.2 Holding time tH 15 6.3 Output capacitor CO 15 6.4 Clock input frequency fREFCLK 16 6.5 Clock input amplitude VREFCLK 17 6.6 Output wideband spurious-free dynamic range SFDRW 18 6.7 Output narrowband spurious-free dynamic range SFDRN 19 6.8 Channel isolation ISO CH 20 6.9 Output amplitude matching error between channels ΔACH 22 6.10 Phase difference between channels ΔPCH 22 6.11 Phase noise 23 6.12 Noise power spectral density24 6.13 Power consumption PW 25 6.14 Supply current ICC 27

Foreword

This document complies with the provisions of GB/T 1.1-2020 "Standardization Work Guidelines Part 1.Structure and Drafting Rules of Standardization Documents" Drafting. Please note that some content in this document may be subject to patents. The publisher of this document assumes no responsibility for identifying patents. This document is proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This document is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78). This document was drafted by. Chengdu Zhenxin Technology Co., Ltd., China Electronics Technology Standardization Institute. The main drafters of this document. He Shanliang, Pu Jia, Yang Yang, Liu Jizu, Fan Chao, Wu Miao, Wang Ke, and Li Kun. Semiconductor integrated circuit Direct digital frequency synthesizer test method

1 Scope

This document specifies a general test method for the electrical characteristics of direct digital frequency synthesizers (hereinafter referred to as "devices") in semiconductor integrated circuits. This document is applicable to the testing of single-channel and multi-channel direct digital frequency synthesizer circuits.

2 Normative reference documents

The contents of the following documents constitute essential provisions of this document through normative references in the text. Among them, the dated quotations For undated referenced documents, only the version corresponding to that date applies to this document; for undated referenced documents, the latest version (including all amendments) applies to this document. GB/T 17574-1998 Semiconductor devices integrated circuits Part 2.Digital integrated circuits

3 Terms and definitions

The following terms and definitions apply to this document. 3.1 Full-scale output current ful-scaleoutputcurrent IFS Configure the output current when the analog output terminal is full scale output. 3.2 gain errorgainerror EG For voltage or current output type devices, the device converts the deviation between the actual output range of the voltage or current and the ideal output range. 3.3 ΔACH Under the same input amplitude configuration of each output channel of a multi-channel device, the absolute value of the maximum deviation between output amplitudes is the same as the smallest absolute value of each channel. The percentage of the output amplitude value. 3.4 Output offset current outputcurrentoffset Configure the output current when the analog output terminal is zero output. 3.5 Output capacitance outputcapacitance CO The capacitance value at the output of the device under specified conditions. ......

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