GB/T 36474-2018 English PDF

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GB/T 36474-2018: Semiconductor integrated circuit -- Measuring methods for double data rate 3 synchronous dynamic random-access memory (DDR3 SDRAM)
Status: Valid

Standard ID	USD	BUY PDF	Lead-Days	Standard Title (Description)	Status
GB/T 36474-2018	359	Add to Cart	4 days	Semiconductor integrated circuit -- Measuring methods for double data rate 3 synchronous dynamic random-access memory (DDR3 SDRAM)	Valid

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Basic data

Standard ID: GB/T 36474-2018 (GB/T36474-2018)
Description (Translated English): Semiconductor integrated circuit -- Measuring methods for double data rate 3 synchronous dynamic random-access memory (DDR3 SDRAM)
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: L56
Classification of International Standard: 31.200
Word Count Estimation: 18,191
Date of Issue: 2018-06-07
Date of Implementation: 2019-01-01
Issuing agency(ies): State Administration for Market Regulation, China National Standardization Administration

GB/T 36474-2018: Semiconductor integrated circuit -- Measuring methods for double data rate 3 synchronous dynamic random-access memory (DDR3 SDRAM)

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Semiconductor integrated circuit--Measuring methods for double data rate 3 synchronous dynamic random access memory (DDR3 SDRAM) ICS 31.200 L56 National Standards of People's Republic of China Semiconductor integrated circuit Third Generation Double Data Rate Synchronous Dynamic Randomization Memory (DDR3 SDRAM) Test Method Memory(DDR3SDRAM) Published on.2018-06-07 2019-01-01 Implementation National Market Supervision Administration China National Standardization Administration released Directory Preface III 1 Scope 1 2 Normative references 1 3 Terms and Definitions 1 4 General requirements 2 4.1 General Rule 2 4.2 General Requirements for Functional Verification 2 4.3 Test Parameters for Electrical Parameters Test 2 4.4 Electrical Parameters Test Oscilloscope 2 4.5 Test Environment 2 5 Detailed Request 3 5.1 Functional Verification 3 5.2 Clock 3 5.3 Reading Data Parameter 6 5.4 write data parameters 8 5.5 Supply Current (IDD)/Data Pin Supply Current (IDDQ) 11

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009. Please note that some of the contents of this document may involve patents. The issuing agency of this document does not assume responsibility for identifying these patents. This standard was proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This standard is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78). This standard was drafted by. China Electronics Standardization Institute, Xi'an Ziguang Guoxin Semiconductor Co., Ltd., Shanghai High Performance Integrated Power Road Design Center, Wuhan Core Technology Co., Ltd., and Chengdu Hua Microelectronics Technology Co., Ltd. The main drafters of this standard. Kong Xianwei, Yin Mengdi, Yin Ping, Ju Peng Jin, College, Liu Jianming. Semiconductor integrated circuit Third Generation Double Data Rate Synchronous Dynamic Randomization Memory (DDR3 SDRAM) Test Method

1 Scope

This standard specifies the functional verification of the third generation double data rate synchronous dynamic random access memory (DDR3 SDRAM) for semiconductor integrated circuits. Identification and electrical parameter testing methods. This standard applies to the third generation of double data rate synchronous dynamic random access memory (DDR3 SDRAM) in the field of semiconductor integrated circuits. Functional verification and electrical parameter testing.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this article Pieces. For undated references, the latest version (including all amendments) applies to this document. GB/T 17574-1998 Semiconductor device integrated circuit Part 2. Digital integrated circuits

3 Terms and Definitions

The following terms and definitions apply to this document. 3.1 Device under test deviceundertest; DUT Tested object during the test. 3.2 Automatic test system automatictestequipment;ATE Integrated integrated circuit test system. Automatic test system with multiple power supplies, digital test channels and dedicated test software Development environment. 3.3 Engineering Evaluation Board evaluationboard; EVB Test engineering evaluation board for functional verification. Engineering Evaluation Board Supports Processor Basic and Extended Functions with Input Output Port, and leave the necessary test interface. 3.4 Double data rate doubledatarate;DDR The architecture of two data transmissions in each clock cycle transfers data on the rising and falling clock edges, respectively. 3.5 Synchronous Dynamic Random Access Memory synchronousdynamicrandomaccessmemory; SDRAM With the clock as the data synchronization reference, it is necessary to continuously refresh the stored data and randomly specify the memory that stores the address. ......

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