JJG 957-2015 English PDF

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JJG 957-2015: Verification Regulation of Logic Analyzers
Status: Valid

JJG 957: Historical versions

Standard ID	USD	BUY PDF	Lead-Days	Standard Title (Description)	Status
JJG 957-2015	669	Add to Cart	5 days	Verification Regulation of Logic Analyzers	Valid
JJG 957-2000	639	Add to Cart	5 days	Verification Regulation of Logic Analyzer	Obsolete

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Basic data

Standard ID: JJG 957-2015 (JJG957-2015)
Description (Translated English): Verification Regulation of Logic Analyzers
Sector / Industry: Metrology & Measurement Industry Standard
Classification of Chinese Standard: A56
Classification of International Standard: 17.220
Word Count Estimation: 29,267
Date of Issue: 2015-08-24
Date of Implementation: 2016-02-24
Older Standard (superseded by this standard): JJG 957-2000
Regulation (derived from): AQSIQ Announcement 2015 No.106
Issuing agency(ies): General Administration of Quality Supervision, Inspection and Quarantine
Summary: This standard applies to the first verification, subsequent verification and in-service inspection of the logic analyzer.

JJG 957-2015: Verification Regulation of Logic Analyzers

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Verification Regulation of Logic Analyzers State verification procedures People's Republic of China Logic Analyzers LogicAnalyzers Issued on. 2015-08-24 2016-02-24 implementation The State Administration of Quality Supervision, Inspection and Quarantine released Logic analyzer test procedures Replacing JJG 957-2000 Focal point. the National Radio Technical Commission metering Drafted by. China Aerospace Science and Industry Corporation Second Hospital 203 This procedure commissioned the National Radio Technical Commission responsible for the interpretation of measurement The drafters of the regulations. Chen Dongqing (China Aerospace Science and Industry Corporation hospital 203) Gongpeng Wei (China Aerospace Science and Industry Corporation hospital 203) Xie (China Aerospace Science and Industry Corporation hospital 203)

table of Contents

Introduction (Ⅱ) 1 Scope (1) 2 Overview (1) 3 metering performance requirements (1) 3.1 Timing Analysis (1) 3.2 State Analysis (1) 4 General Requirements (1) 4.1 Appearance and Accessories (1) 4.2 of the work (1) 5 control of measuring instruments (1) 5.1 test conditions (1) 5.2 Verification Project (2) 5.3 Verification Methods (3) 5.4 Verification Results Processing (9) 5.5 test cycle (9) Appendix A in-page original record format (10) Appendix B test certificate-page format (15) Appendix C test results in the notice page format (20)

Introduction

This procedure is JJG 957-2000 "logic analyzer test procedures" amendments. Procedures based JJF1002-2010 "National verification procedures to write the rules," revised. The main technical changes are as follows. --- The original statutes timing analysis and state analysis speed clock rate has been extended, were the original 100MHz Up to 5GHz and 50MHz up to 2GHz; --- The original statutes minimum clock pulse width is extended, the original 5ns to 200ps; --- Setup and data in the original protocol data retention time is measured has been revised, the original 0ns ~ 50ns to setup/hold time window measuring range of 180ps ~ 10ns; --- The original regulations can be detected in the narrowest width of the glitch has been revised, the original 0.5ns to 1ns; --- The original statutes threshold level measurement range has been revised to former -20V ~ 20V -10V ~ 10V; --- The original statutes verification project was amended to remove the highest clock mixed mode operation state analysis Clock rate test, the new increase minimum pulse width (200ps) and time intervals (≥1ns) verification. The regulations previously issued as follows. --- JJG 957-2000. Logic analyzer test procedures

1 Scope

The order applies to the logic analyzer's initial verification, use and subsequent verification check.

2 Overview

Logic analyzer is mainly used for debugging hardware and software of a digital circuit having a plurality of data channels and a plurality of synchronous clock Characteristics that can facilitate the analysis of digital logic circuits. Divided into logical signals from the principle of timing analysis and logic State analysis of the signal by the multiplexer logic probe input data signal to logic "1" to "0" data status display. can Multi-stage trigger to collect data, you can display a list of the status of data collection mode or wave mode.

3 metering performance requirements

3.1 Timing Analysis a) threshold level. -10V ~ 10V, the maximum permissible error. ± (1% × reading 35mV); b) minimum pulse width.200ps (maximum clock speed 5GHz); c) glitch detection width. 1ns; d) Time interval measurement. ≥1ns, the maximum permissible error. ± (0.01% × reading a sampling period). 3.2 Status Analysis a) state the maximum clock speed. 2GHz; b) state the minimum clock pulse width.200ps; c) the data setup/hold time window (Tw). 180ps ~ 10ns.

4 General technical requirements

4.1 Exterior Accessories Logic analyzer should look good, no effect on normal work of mechanical damage. Power supply clear signs, and set Set correctly. Accessories and operating instructions should be complete. 4.2 The normal sex After energizing the logic analyzer screen should be normal, all the switches, buttons and knobs should be solid and reliable installation, location Accurate, good contact, smooth adjustment after the Power On Self Test by various indicators show should be normal.

5 control of measuring instruments

5.1 verification Conditions 5.1.1 Environmental conditions Verification a) Ambient temperature. 23 ℃ ± 5 ℃; b) Relative humidity. ≤80%; c) Power supply. 220V ± 11V, 50Hz ± 1Hz; ......

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