GB/T 37979-2019 English PDF

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GB/T 37979-2019: Safe rule of VHDL for programmable logic device software
Status: Valid

Standard ID	USD	BUY PDF	Lead-Days	Standard Title (Description)	Status
GB/T 37979-2019	839	Add to Cart	7 days	Safe rule of VHDL for programmable logic device software	Valid

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Basic data

Standard ID: GB/T 37979-2019 (GB/T37979-2019)
Description (Translated English): Safe rule of VHDL for programmable logic device software
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: L77
Classification of International Standard: 35.080
Word Count Estimation: 42,426
Date of Issue: 2019-08-30
Date of Implementation: 2020-03-01
Issuing agency(ies): State Administration for Market Regulation, China National Standardization Administration

GB/T 37979-2019: Safe rule of VHDL for programmable logic device software

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Safe rule of VHDL for programmable logic device software ICS 35.080 L77 National Standards of People's Republic of China Programmable logic device software VHDL programming Safety requirements Published on.2019-08-30 2020-03-01 implementation State market supervision and administration China National Standardization Administration issued

Content

Foreword III 1 Scope 1 2 Normative references 1 3 Terms and Definitions 1 4 Abbreviations 1 5 Security Rules 1 5.1 instantiation class 1 5.2 Structural Design Class 4 5.3 Sensitive List Class 8 5.4 Declaration Definition Class 9 5.5 Named Class 10 5.6 Operation class 13 5.7 Loop Control Class 16 5.8 Branch Control Class 16 5.9 Clock Class 20 5.10 Reset and Initialization Class 26 5.11 State Machine Class 30 5.12 Synthesis/Constraint Class 33 5.13 Annotation Class 35 5.14 Encoding Format Class 36 Reference 37

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009. Please note that some of the contents of this document may involve patents. The issuing organization of this document is not responsible for identifying these patents. This standard is proposed and managed by the National Information Technology Standardization Technical Committee (SAC/TC28). This standard was drafted. 704 Institute of the Third Research Institute of China Aerospace Science and Industry Group, China Electronics Technology Standardization Institute, China Nuclear Control Systems Engineering Co., Ltd., National Space Science Center of the Chinese Academy of Sciences. The main drafters of this standard. Li Lihua, Wang Li, Yang Nan, Wang Dong, Zhu Lin, Zhang Guoyu, Han Xudong, Wang Ying, Yan Lifeng, Liu Wei, Zheng Jinyan, Li Wenpeng, Hu Yiwu, Hu Yong, Hao Yongle, Zhao Jing, Li Chao, Cheng Cheng, Jiang Xiaohui, Yao Xiujuan, Gao Yuan, Huang Yong, Zhang Qing, Zhang Wei, Liu Zhikai, Liang Chenghua, Chen Peng, Zhou Ning, Xu Guangchen, Shi Jie. Programmable logic device software VHDL programming Safety requirements

1 Scope

This standard specifies the safety rules for VHDL software programming for programmable logic devices. This standard applies to the programming safety design, coding, testing and use of programmable logic device software VHDL. ASIC digital circuit It can also be used for reference during design.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this article. Pieces. For undated references, the latest edition (including all amendments) applies to this document. GB/T 11457-2006 Information Technology Software Engineering Terminology GB/T 33781-2017 General requirements for software development of programmable logic devices

3 Terms and definitions

The terms and definitions defined in GB/T 11457-2006 and GB/T 33781-2017 apply to this document.

4 Abbreviations

The following abbreviations apply to this document. FPGA. Field Programmable Gate Array (FieldProgrammableGateArray) VHDL. Very high speed integrated circuit hardware description language (Very-high-speedintegratedcircuitHardwareDescription Language)

5 Security Rules

5.1 instantiation class 5.1.1 Port instantiation should adopt name mapping to avoid location mapping. When port instantiation is performed, name mapping should be adopted to avoid location mapping, which is beneficial to improve the readability and maintainability of the program. Example. Follow the example Port instantiation takes name mapping Reset_filter_inst.reset_filter Portmap(reset_in = >reset_in, Clk = >clk, Reset_out = >reset_out); ......

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