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GB/T 25105.2-2025 English PDF

GB/T 25105.2: Historical versions

Standard IDUSDBUY PDFLead-DaysStandard Title (Description)Status
GB/T 25105.2-2025RFQ ASK 3 days Industrial communication networks - Fieldbus specifications - Type 10: PROFINET IO specifications - Part 2: Application layer protocol specification Valid
GB/T 25105.2-2014RFQ ASK 3 days Industrial communication networks -- Fieldbus specifications -- Type 10 PROFINET IO specifications -- Part 2: Application layer protocol specification Valid

Similar standards

GB/T 20438.5   GB/T 20438.4   GB/T 20438.6   GB/T 25105.1   GB/T 25105.3   GB/T 25105.3   

Basic data

Standard ID: GB/T 25105.2-2025 (GB/T25105.2-2025)
Description (Translated English): Industrial communication networks - Fieldbus specifications - Type 10: PROFINET IO specifications - Part 2: Application layer protocol specification
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: N10
Classification of International Standard: 25.040
Word Count Estimation: 1358,155
Date of Issue: 2025-04-25
Date of Implementation: 2025-11-01
Older Standard (superseded by this standard): GB/T 25105.2-2014
Issuing agency(ies): State Administration for Market Regulation, China National Standardization Administration

GB/T 25105.2-2025: Industrial communication networks - Fieldbus specifications - Type 10: PROFINET IO specifications - Part 2: Application layer protocol specification


---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
ICS 25.040 CCS N10 National Standard of the People's Republic of China 61158-6-10.2023 Replace GB/T 25105.2-2014 Fieldbus Specifications for Industrial Communication Networks Type 10.PROFINET IO Specifications Part 2.Application layer protocol specification Industrial Type 10. PROFINET IO Part 2. Application layer specification (IEC Industrial networks-Fieldbus 6-10. Application layer specification- Type IDT) Published on April 25, 2025, implemented on November 1, 2025 State Administration for Market Regulation The National Standardization Administration issued

Table of contents

Preface ⅩLⅨ Introduction 1 Scope 1 1.1 Overview 1 1.2 Specification 1 1.3 Consistency 1 2 Normative references 1 3 Terms, Definitions, Symbols, Abbreviations and Conventions 5 3.1 Referenced terms and definitions 6 3.2 Terms and Definitions 7 3.3 Abbreviations and symbols 15 3.4 Agreement 22 4 Application layer protocol specifications for common protocols 37 4.1 FAL Syntax Description 37 4.2 Transfer Syntax 41 4.3 Discovery and Basic Configuration 67 4.4 Precision Transparent Clock Protocol 127 4.5 Time Synchronization 216 4.6 Media Redundancy 222 4.7 Real-time loop 225 4.8 Real-time Acyclic 261 4.9 Segment 336 4.10 Remote Procedure Call 354 4.11 Link Layer Discovery 373 4.12 Terminal Stations and Bridges 387 4.13 IP Suite 522 4.14 Domain Name System 529 4.15 Dynamic Host Configuration 530 4.16 Simple Network Management 533 4.17 Network Configuration 535 4.18 General DLL Mapping Protocol Machine 538 4.19 Blank 549 4.20 Other Information 549 61158-6-10.2023 5 Application Layer Protocol Specification for Distributed I/O 549 5.1 FAL Syntax Description 549 5.2 Transfer Syntax 584 5.3 FAL Protocol State Machine 853 5.4 AP-Context State Machine 854 5.5 FAL Service Protocol Machine 854 5.6 Application Relationship Protocol Machine 886 5.7 DLL Mapping Protocol Machine 1157 5.8 Checking Rules 1157

Appendix A

(Normative) Unified establishment of all RT ARs 1203 A.1 Overview 1203 A.2 AR established 1204 A.3 Startup of alarm sender and receiver 1211 A.4 Time-aware system path establishment 1213

Appendix B

(Normative) Compatible with AR build 1215

Appendix C

(Informative) Device access AR establishment 1218

Appendix D

(Informative) AR establishment (acceleration process) 1220

Appendix E

(Informative) AR establishment (quick start process) 1223

Appendix F

(Informative) Upload, storage and retrieval process example 1225

Appendix G

(Informative) Implementation of Send List Control 1227 G.1 Overview 1227 G.2 Implementation Model 1228 G.3 Constraints 1229

Appendix H

(Informative) Overview of IO controller and IO device state machines 1231 Appendix I (Informative) Overview of the PTCP Synchronous Master Hierarchy 1233 Appendix J (Informative) Bandwidth usage optimization for time-aware shaping 1235 Appendix K (Informative) RT_CLASS_3 bandwidth allocation time limit 1237 Appendix L (Informative) Time limit for frame forwarding 1239 L.1 Principle 1239 L.2 Forward 1239 Appendix M (Informative) Dynamic frame packaging principle 1241 Appendix N (Informative) Segmentation Principle 1244 Appendix O (Informative) MRPD---Seamless Media Redundancy Principle 1246 Appendix P (Informative) RED_RELAY principle 1248 without forwarding information in PDIRFrameData Appendix Q (Informative) Auto-negotiation limit 1250 Q.1 Fast Startup Optimized 1250 without Auto-Negotiation Q.2 Gigabit PHY, 2-pair Ethernet cable, and auto-negotiation 1251 61158-6-10.2023 Appendix R (Informative) PrmBegin, PrmEnd, and ApplRdy Sequence Example 1253 Appendix S (Informative) Supported MIB List 1254 Appendix T (Informative) BLOB structure and content 1255 Appendix U (Normative) Management Information Base 1256 U.1 Void 1256 U.2 LLDP EXT MIB 1256 Appendix V (Normative) To IEC Cross reference 1292 to 62439-2 V.1 for IEC Cross reference 1292 to 62439-2 Appendix W (Normative) Ethernet Statistics Counter Maintenance 1296 W.1 Overview 1296 W.2 Counting Model 1296 W.3 IETF Explanation of Statistics Counters Defined by RFC 1298 W.4 IETF The value range of the statistics counter defined by RFC 1299 W.5 VLAN-specific statistics counters 1299 Appendix X (Informative) RSI Segment Example 1300 Appendix Y (Informative) Delayed direct access 1302 Reference 1304 Figure 1 General structure of specific fields for octet 1 23 FIG2 Specific fields general structure 24 for octet 2 FIG3 Generic structure of specific fields for octet 3 24 Figure 4.Generic structure of specific fields for octet 4.25 Figure 5 Generic structure of specific fields for octet 5 25 FIG6 Generic structure 26 of the specific fields for octet 6 FIG. 7 Generic structure 26 of specific fields for octet 7 Figure 8.Generic structure of specific fields for octet 8. Figure 9.Generic structure of specific fields for octet 9.27 FIG10 Specific fields general structure 28 for octet 10 FIG11 Specific fields general structure 28 for octet 11 FIG12 Specific fields general structure 29 for octet 12 Figure 13.Generic structure of specific fields for octet 13.29 FIG. 14.General structure 30 for specific fields of octet 14. FIG15 Specific fields general structure 30 for octet 15 FIG16 Generic structure 31 of specific fields for octet 16 Figure 17 Encoding of BinaryDate data type 42 Figure 18 Encoding of a TimeOfDay value with a date indication 43 Figure 19 Encoding of a TimeOfDay value without a date indication43 61158-6-10.2023 Figure 20 TimeDifference with date indication Value encoding 44 Figure 21 Encoding of TimeDifference value without date indication 44 Figure 22 NetworkTime value encoding 45 Figure 24 Encoding of TimeStamp value 47 Figure 25 Encoding of TimeStampDifference value 48 Figure 28 Stream destination MAC address --- StreamDA 58 Figure 29 DCPUCS state transition diagram 103 Figure 30 DCPUCR state transition diagram 109 Figure 31 DCPMCS state transition diagram 116 Figure 32 Basic structure of DCP multicast receiver 119 Figure 33 DCPMCR state transition diagram 120 Figure 34 DCPHMCS state transition diagram 124 Figure 35 DCPHMCR state transition diagram 126 Figure 36 PTCP_SequenceID value range 131 Figure 37 Message timestamp point 138 Figure 38 Timer model 138 Figure 39 4 message timestamps 139 Figure 40 Line delay protocol 140 with follow-up frame Figure 41 Line delay protocol without follow-up frame 140 Figure 42 Line delay measurement 142 Figure 43 Model parameters for GSDML usage 144 Figure 44 Bridge delay measurement 145 Figure 45 PTCP delay accumulation 146 Figure 46 PTP delay accumulation 146 Figure 47 Worst case cumulative synchronization time deviation 147 Figure 48 Signal generation for deviation measurement 147 Figure 49 Deviation measurement 148 Figure 50 PTCP master sends no Follow Up-Frame's Sync-Frame 149 Figure 51 PTCP master sends Sync-Frame with FollowUp-Frame 149 Figure 52 FU synchronization slave 150 forwarding Sync-Frame Figure 53 FU synchronization slave 151 forwarding Sync- and FollowUp-Frame Figure 54 FU synchronization slave 152 forwarding the Sync- and generated FollowUp-Frame Figure 55 Monitoring principle of line delay measurement 153 Figure 56 DELAY_REQ state transition diagram 155 61158-6-10.2023 Figure 57 DELAY_RSP state transition diagram 165 Figure 58 PTCP Overview 170 Figure 59 SYN_BMA state transition diagram 173 Figure 60 SYN_MPSM state transition diagram 186 Figure 61 SYN_SPSM state transition diagram 194 Figure 62 SYNC_RELAY state transition diagram 203 Figure 63 SCHEDULER state transition diagram 211 Figure 64 Station clock model 217 Figure 65 Time Synchronized Terminal Station Model 218 Figure 66 GlobalTime timer model 219 Figure 67 WorkingClock timer model 220 Figure 68 Non-time-aware system --- WorkingClock and Figure 69 Time-aware system --- queue shielding --- WorkingClock and CycleCounter 221 Figure 70 Time perception system --- WorkingClock and CycleCounter 221 Figure 71 Media redundancy --- Ring 222 Figure 72 Media redundancy --- interconnection 224 Figure 73 Cycle Counter (CycleCounter) value range 227 Figure 74 CycleCounter structure 228 Figure 75 Optimized CycleCounter settings 228 Figure 76 SFCRC16 generation rules 232 Figure 77 SFCycleCounter value range 233 Figure 78 Overview of the buffer life cycle model 236 Figure 79 PPM flow model 236 Figure 80 CPM flow model 237 Figure 81 Basic structure of PPM with frame structure 238 Figure 82 Basic structure of PPM with subframe structure 239 Figure 83 PPM state transition diagram 241 Figure 84 Basic structure of CPM 246 Figure 85 CPM state transition diagram 249 Figure 86 RTA addressing mechanism 263 Figure 87 APM structure 274 Figure 88 Structure of RSI 274 Figure 89 APMS structure 275 Figure 90 APMS state transition diagram 277 Figure 91 APMR structure 284 Figure 92 APMR state transition diagram 286 Figure 93 RSII state transition diagram 293 61158-6-10.2023 Figure 94 RSIIN state transition diagram 310 Figure 95 RSIR state transition diagram 313 Figure 96 RSIRN state transition diagram 332 Figure 97 FRAG_D state transition diagram 343 Figure 98 FRAG_S state transition diagram 347 Figure 99 DEFRAG state transition diagram 351 Figure 100 DLL Mapping Protocol Machine (DMPM) 387 Figure 101 Schematic diagram of data flow of control loop 388 Figure 102 Based on IEEE 802.1Q End Station Model 392 Figure 103 Ethernet interface model based on IEEE --- sending direction 393 Figure 104 SendListControl corresponding to the Ethernet interface model 394 Figure 105 Algorithm for the terminal station ETS model 395 Figure 106 Credit-based Shaper Algorithm 397 Figure 107 Send List Feed 399 Figure 108 Relationship between bandwidth and SendClock@10 Mbit/s 401 Fig.109 10 SendClock adaption 401 at Mbit/s Figure 110 Relationship between bandwidth and SendClock @100 Mbit/s 401 Figure 111 Relationship between bandwidth and SendClock@1 Gbit/s 402 Figure 112 Queue shielding --- time-aware terminal station --- non-time-aware flow 406 Figure 113 Queue shielding --- time-aware terminal station --- with time-aware flow 408 Figure 114 Queue shielding --- non-time-aware terminal station --- no RT_CLASS_3 410 Figure 115 Queue shielding --- non-time-aware terminal station --- with RT_CLASS_3 412 Figure 116 Terminal Station 413 Figure 117 End station system---having multiple end station components 414 Figure 118 System 415 including bridge Figure 119 Domain Boundary 416 Figure 120 Domain boundary --- RT_CLASS_STREAM, class RT 417 Figure 121 Domain boundary --- boundary port 418 Figure 122 Domain boundary --- NME domain flow 419 Figure 123 LLC protocol flow 422 Figure 124 Ingress rate limiter --- domain boundary 432 Figure 125 Ingress rate limiter --- domain boundary 436 Figure 126 Schematic diagram of the communication flow model of the bridge 439 Figure 127 Time-aware system---bridge egress port resource model 444 Figure 128 Non-time-aware system --- bridge egress port resource model 445 Figure 129 Bridge queue masking usage model 451 Figure 130 RED_RELAY --- Bridge queue masking usage model 452 61158-6-10.2023 Figure 131 TAS settings --- bridge queue masking model 453 Figure 132 RED_RELAY settings --- queue masking model 453 Figure 133 Bridge 456 with terminal station Figure 134 Transmission---Bridge port 457 Figure 135 Forwarding process --- Bridge 458 Figure 136 Receiving --- Bridge port 458 Figure 137 Transmission---Management port 459 Figure 138 Receive --- Management port 460 Figure 139 Bridge terminal station 461 Figure 140 Bridge terminal station interface model consistent with IEEE 462 Figure 141 Bridge terminal station system reference figure 463 Figure 142 Sending List Principles 464 Figure 143.WorkingClock response in case of synchronization loss/resynchronization 465 Figure 144 Bridge terminal station 466 with proprietary interface Figure 145 Internal and external reference surfaces 467 Figure 146 Forwarding bridge resources versus dedicated bridge resources 467 Figure 147.Bridge end stations with multiple entities—one end station per bridge component 468 Figure 148 Bridge end stations with multiple entities - each bridge component has multiple end stations 468 Figure 149 QPSM state transition diagram 470 Figure 150 PPSM state transition diagram 476 Figure 151 RTC3PSM state transition diagram 480 Figure 152 State transition diagram of generated events 485 Figure 153 RED_RELAY state transition diagram 487 Figure 154 DFP_RELAY mechanism 491 Figure 155 DFP_RELAY_INBOUND and DFP_RELAY_IN_STORAGE mechanisms 492 Figure 156 DFP_RELAY_OUTBOUND mechanism 492 Figure 157 DFP_RELAY state transition diagram 494 Figure 158 DFP_RELAY_INBOUND state transition diagram 497 Figure 159 DFP_RELAY_IN_STORAGE state transition diagram 502 Figure 160 DFP_RELAY_OUTBOUND state transition diagram 507 Figure 161 MUX state transition diagram 512 Figure 162 DEMUX state transition diagram 518 Figure 163 ACCM state transition diagram 527 Figure 164 DHCP state transition diagram 531 Figure 165 Network management entity 536 Figure 166 NMAD model for network management 537 Figure 167 YANG model of bridge component 537 61158-6-10.2023 Figure 168 YANG model 538 of the terminal station component Figure 169 Protocol machine structure in DMPM (bridge) 539 Figure 170 LMPM state transition diagram 543 Figure 172 FrameSendOffset and cycle duration 669 Figure 173 Severity classification for faults, maintenance, and normal operations 730 Figure 174 Update interval measurement 736 Figure 175 Cut-off time measurement 737 Figure 177 RR 1 Chronograph Model 739 Figure 178 RR 4 Chronograph Model 740 Figure 179 Principle of calculation of cycle 747 Figure 180 Calculation principle of minimum YelowTime 748 Figure 181 Example of IPG behavior of ideal end station components under emergency conditions 783 Figure 182 Example of IPG behavior of end station components in emergency situations 784 Figure 183 Lost frame detection --- 794 appears Figure 184 Lost frame detection --- disappearance 794 Figure 185 Definition of retention time interval 813 Figure 186 Top view of the PLL window 816 Figure 187 Definition of PLL window 817 Figure 188 Time PLL The top view of the window 819 Figure 189 Time PLL Definition of window819 Figure 190 DFP delay error detection --- appearance and disappearance 830 Figure 192 Endpoint1 and Endpoint2 schemes --- upper and lower 834 Figure 193 Endpoint1 and Endpoint2 scheme --- left and right 834 Figure 194 Relationship between protocol machines 853 Figure 195 ALPMI state transition diagram 888 Figure 196 ALPMR state transition diagram 894 Figure 197 IO device CM integration solution 899 Figure 198 IO device CM state transition diagram 901 Figure.199 CMDEV state transition diagram 906 Figure.200 IO device CM-device access mechanism 913 Figure.201 CMDEV_DA state transition diagram 915 Figure 202 CMSU state transition diagram 921 Figure 203 CMIO state transition diagram 928 Figure 204 CMRS state transition diagram 932 61158-6-10.2023 Figure 205 CMWRR state transition diagram 936 Figure 206 CMRDR state transition diagram 943 Figure 207 CMSM state transition diagram 946 Figure 208 CMPBE state transition diagram 951 Figure 209 CMDMC state transition diagram 957 Figure 210 CMINA state transition diagram 963 Figure 211 CMRPC state transition diagram 970 Figure 212 Intersection and remaining amount using different ARUUID.ConfigID 980 Figure 213 Intersection and deletion amount using different ARUUID.ConfigID 981 Figure 214 CMSRL state transition diagram 982 Figure 215 Single input and single output buffer of CMSRL 990 Figure 216 Dynamic reconfiguration of CMSRL 991 Figure 217 CMSRL alarm queue management 991 Figure 218 CMSRL Reporting System Management 992 Figure 219 Primary. Switching time between two ARs of ARset993 Figure 220 Backup. Switching time between two ARs of ARset993 Figure 221 CMSRL_AL state transition diagram 995 Figure 222 CMRSI state transition diagram 1001 Figure 223 IO controller CM scheme 1007 Figure 224 IO controller CM state transition diagram 1009 Figure 225 CMCTL state transition diagram 1015 Figure 226 CTLSM state transition diagram 1025 Figure 227 CTLIO state transition diagram 1029 Figure 228 CTLRDI state transition diagram 1035 Figure 229 CTLRDR state transition diagram 1039 Figure 230 CTLRPC state transition diagram 1046 Figure 231 CTLSU state transition diagram 1054 Figure 232 CTLWRI state transition diagram 1061 Figure 233 CTLWRR state transition diagram 1068 Figure 234 CTLPBE state transition diagram 1072 Figure 235 CTLDINA state transition diagram 1079 Figure 236 Automatic NameOfStation (station name) allocation 1087 Figure 237 CTLSRL state transition diagram 1089 Figure 238 CTLSRL input and output buffers 1094 Figure 239 Dynamically reconfigured input and output buffers 1095 Figure 240 Alarm queue management of CTLSRL 1095 Figure 241 Dynamically reconfigured alarm queue management 1096 61158-6-10.2023 Figure 242 CTLSC state transition diagram 1097 Figure 243 CTLRSI state transition diagram 1104 Figure 244 Network Management Engine Manager Scheme 1110 Figure 245 Scheme 1114 of the station carrying CIM and NME Figure 246 Scheme 1114 of the station carrying CIM and query flow Figure 247 Scheme 1115 of a station that only carries CIM Figure 248 NME state transition diagram 1120 Figure 249 TDE state transition diagram 1129 Figure 250 PCE state transition diagram 1133 Figure 251 NCE state transition diagram 1138 Figure 252 NUE state transition diagram 1143 Figure 253 BNME state transition diagram 1151 Figure 254 NMEINA state transition diagram 1154 Figure A.1 AR establishment (initial connection) using RT_CLASS_1, RT_CLASS_2 or RT_CLASS_3 Monitoring w/o RT) 1204 Figure A.2 AR establishment using RT_CLASS_1, RT_CLASS_2 or RT_CLASS_3 (using RT Connection monitoring) 1205 Figure A.3 Principle of data evaluation during startup (RED channel setup delay) 1206 Figure A.4 Principle of data evaluation during startup (RED channel established immediately) 1207 Figure A.5 Principle of data evaluation during startup (special case. Isochronous mode applications) 1208 Figure A.6 AR establishment using RSI 1209 Figure A.7 Building an AR application using streaming and synchronization mode 1210 Figure A.8 Startup of alarm sender and receiver without system redundancy 1211 Figure A.9 Startup of alarm sender and receiver with system redundancy 1212 Figure A.10 Activation of alarm sender and receiver during PrmBegin/PrmEnd/ApplRdy sequence 1213 Figure A.11 Time-aware system path establishment 1214 Figure B.1 Using RT_CLASS_3 AR (startup mode "Legacy") AR build 1216 Figure B.2 Using RT_CLASS_1, 2 or UDP AR (startup mode "Legacy") AR build 1217 Figure C.1 Establishment of device access AR 1218 Figure C.2 Establishment of access to AR using RSI device 1219 Figure D.1 Accelerated build of error-free IOAR 1221 Figure D.2 IOAR accelerated build 1222 with “delay error” Figure E.1 IOAR setup using quick start 1224 Figure F.1 Example of uploading from storage 1225 Figure F.2 Example of retrieving from storage 1226 Figure G.1 Application queues required to implement frequency reduction ratio 1228 Figure G.2 Application queues requir......
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