GB/T 7092-2021 English PDF

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GB/T 7092-2021: Outline dimensions of semiconductor integrated circuits
Status: Valid

GB/T 7092: Historical versions

Standard ID	USD	BUY PDF	Lead-Days	Standard Title (Description)	Status
GB/T 7092-2021	7289	Add to Cart	25 days	Outline dimensions of semiconductor integrated circuits	Valid
GB/T 7092-1993	RFQ	ASK	6 days	Outline dimensions of semiconductor integrated circuits	Obsolete

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Basic data

Standard ID: GB/T 7092-2021 (GB/T7092-2021)
Description (Translated English): Outline dimensions of semiconductor integrated circuits
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: L55
Word Count Estimation: 394,319
Issuing agency(ies): State Administration for Market Regulation, China National Standardization Administration

GB/T 7092-2021: Outline dimensions of semiconductor integrated circuits

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Outline dimensions of semiconductor integrated circuits ICS 31.200 L55 National Standards of People's Republic of China Replace GB/T 7092-1993 Overall dimensions of semiconductor integrated circuits Released on 2021-03-09 2021-10-01 implementation State Administration of Market Supervision and Administration Issued by the National Standardization Management Committee

Table of contents

Foreword Ⅲ 1 Scope 1 2 Normative references 1 3 Package outline 1 3.1 Metal package 1 3.2 Ceramic package 1 3.3 Plastic package 2 4 Dimensions and tolerances 3 5 Package outline classification and coding 4 6 Product outline drawing and size parameters 4 6.1 General 4 6.2 Metal cylindrical package 4 6.3 Metal diamond package (F-1, F-2) 5 6.4 Metal flange package (TO-254, TO-257) 7 6.5 Metal pad package (SMD-0.5, SMD-1) 8 6.6 Ceramic Dual In-line Package (CDIP) 10 6.7 Ceramic glass fused dual in-line package (GDIP) 13 6.8 Ceramic Leadless Chip Carrier Package (CLCC) 15 6.9 Ceramic Flat Package (CFP) 22 6.10 Ceramic glass fused flat package (GFP) 24 6.11 Ceramic dual-row no-lead flat package (CDFN) 26 6.12 Ceramic Small Outline Package (CSOP) 29 6.13 Ceramic glass fused small outline package (GSOP) 34 6.14 Ceramic Quad Flat Package Series 35 6.15 Ceramic Pin Grid Array Package (CPGA) 49 6.16 Ceramic Pin Grid Array Package (Staggered) (CIPGA) 52 6.17 Ceramic Land Array Package (CLGA) 54 6.18 Ceramic Ball Array Package (CBGA) 72 6.19 Ceramic Pillar Array Package (CCGA) 91 6.20 Plastic Cylindrical Package (TO-92) 105 6.21 Plastic flange package series 106 6.22 Plastic single in-line package series 120 6.23 Plastic dual in-line package series 122 6.24 Plastic dual-row no-lead flat package series (PVDFN, PWDFN, PUDFN, PXDFN) 130 6.25 Plastic small outline package series (first category) 140 6.26 Plastic Small Outline Package Series (Class 2) 146 6.27 Plastic Quad Flat Package Series 176 6.28 Plastic four-side leadless flat package series (PQFN, PLQFN, PTQFN, PVQFN, PWQFN, PUQFN, PXQFN, PPQFN) 197 6.29 Plastic land array package series (PLGA, PLLGA, PTLGA, PVLGA, PWLGA, PULGA, PXLGA) 6.30 Plastic solder ball array package series (PB1BGA, PBBGA, PBGA, PLBGA, PTBGA, PVBGA, PWBGA, PUBGA, PXBGA) 299 Appendix A (informative appendix) Description of package outline changes 385 Appendix B (normative appendix) Outline dimension symbol description 386 Appendix C (informative appendix) Simple identification code of package outline 390

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009. This standard replaces GB/T 7092-1993 "Semiconductor Integrated Circuit Dimensions", and the main technical changes compared with GB/T 7092-1993 Change as follows. ---Modified the packaging outline coding rules, and the content quoted GB/T 15879.4-2019 (see Chapter 5, Appendix A of the.1993 edition); ---Modified the package shape classification, and added a number of metal packages, ceramic packages and plastic packages. For details, see Appendix A; ---Modified the outline dimension symbol description (see Appendix B, Appendix B of the.1993 edition); ---The simple identification code of the package shape has been added (see Appendix C). Please note that some of the contents of this document may involve patents. The issuing agency of this document is not responsible for identifying these patents. This standard was proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This standard is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78). Drafting organizations of this standard. China Electronics Standardization Institute, Tongfu Microelectronics Co., Ltd., Tianshui Huatian Technology Co., Ltd. Company, Jiangsu Changdian Technology Co., Ltd., Wuxi China Resources Ansheng Technology Co., Ltd., China Electronics Technology Group Corporation 58th Research Institute, Jiangsu Yixing Electronic Devices Factory Co., Ltd., Fujian Minhang Electronics Co., Ltd., China Electronics Technology Group Corporation 47th Research Institute, the 772th Research Institute of the Ninth Research Institute of China Aerospace Science and Technology Corporation, the 13th Research Institute of China Electronics Technology Group Corporation, Qingdao Kairui Electronics Co., Ltd. The main drafters of this standard. An Qi, Shi Lei, Ji Yonggang, Lin Xingjiang, Li Xizhou, Xu Feng, Zhou Ganying, Tong Liangyu, Ding Rongzheng, Xu Mengjiao, Shi Liying, Shao Kang, Yu Yongmei, Tian Aimin, Jing Linxiao, Bloomberg, Li Lixia, Chen Xiangbo, Li Jingjing, Li Kun, Yin Hang, Wang Baoyou, Zhang Yuqin. The previous versions of the standard replaced by this standard are as follows. ---GB 7092-1986, GB/T 7092-1993. Overall dimensions of semiconductor integrated circuits

1 Scope

This standard specifies the packaging form and dimensions of semiconductor integrated circuits. This standard applies to the packaging design and finished product size inspection of semiconductor integrated circuits. This standard does not apply to hybrid integrated circuits.

2 Normative references

The following documents are indispensable for the application of this document. For dated reference documents, only the dated version applies to this article Pieces. For undated reference documents, the latest version (including all amendments) is applicable to this document. GB/T 1182 Geometric Technical Specification for Products (GPS) Geometric Tolerance Shape, Direction, Position and Runout Tolerance Marking GB/T 1958 Product Geometric Technical Specification (GPS) Geometric Tolerance Testing and Verification GB/T 15879.4-2019 Mechanical standardization of semiconductor devices Part 4.Classification and coding system of semiconductor device package outlines

3 Package outline

3.1 Metal package The main categories of metal package outlines are as follows. a) Metal cylindrical package; b) Metal diamond package series. 1) Metal diamond package (F-1); 2) Metal diamond package (F-2); c) Metal flange package series. 1) Metal flange package (TO-254); 2) Metal flange package (TO-257); d) Metal pad package series. 1) Metal pad package (SMD-0.5); 2) Metal pad package (SMD-1). 3.2 Ceramic package The main categories of ceramic package outlines are as follows. a) Ceramic dual in-line package (CDIP); b) Ceramic glass fused dual in-line package (GDIP); c) Ceramic leadless chip carrier package (CLCC); d) Ceramic flat package (CFP); e) Ceramic glass fused flat package (GFP); f) Ceramic dual-row no-lead flat package (CDFN); g) Ceramic small outline package (CSOP); ......

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