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GB/T 35007-2018 English PDF

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US$759.00 · In stock
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GB/T 35007-2018: Semiconductor integrated circuits -- Measuring method of low voltage differential signaling circuitry
Status: Valid

Standard ID	USD	BUY PDF	Lead-Days	Standard Title (Description)	Status
GB/T 35007-2018	759	Add to Cart	5 days	Semiconductor integrated circuits -- Measuring method of low voltage differential signaling circuitry	Valid

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Basic data

Standard ID: GB/T 35007-2018 (GB/T35007-2018)
Description (Translated English): Semiconductor integrated circuits -- Measuring method of low voltage differential signaling circuitry
Sector / Industry: National Standard (Recommended)
Classification of Chinese Standard: L56
Classification of International Standard: 31.200
Word Count Estimation: 38,317
Date of Issue: 2018-03-15
Date of Implementation: 2018-08-01
Issuing agency(ies): State Administration for Market Regulation, China National Standardization Administration

GB/T 35007-2018: Semiconductor integrated circuits -- Measuring method of low voltage differential signaling circuitry

---This is a DRAFT version for illustration, not a final translation. Full copy of true-PDF in English version (including equations, symbols, images, flow-chart, tables, and figures etc.) will be manually/carefully translated upon your order.
Semiconductor integrated circuits--Measuring method of low voltage differential signaling circuitry ICS 31.200 L56 National Standards of People's Republic of China Semiconductor integrated circuit Low voltage differential signal circuit test method Published by.2018-03-15 2018-08-01 Implementation General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China China National Standardization Administration released Directory Preface III 1 Scope 1 2 Normative references 1 3 Terms and Definitions 1 4 General 2 4.1 Test Environment Requirements 2 4.2 Test Considerations 2 5 Static Parameter Test 2 5.1 Single-Ended Digital Interface Parameters 2 5.2 Input High-Level Threshold Voltage (VTH) 2 5.3 Input Low-Level Threshold Voltage (VTL) 3 5.4 Input Current (IIN) 4 5.5 Power Supply Shutdown Input Current (IIN-OFF) 5 5.6 Output LVDS High Voltage (VOHL) 6 5.7 Output LVDS Low Voltage (VOLL) 7 5.8 Common Mode Output Voltage (VOS) 8 5.9 Compatible Common-Mode Output Voltage Variation (ΔVOS) 8 5.10 Differential Output Voltage (VOD) 9 5.11 Complementary Differential Output Voltage Variation (ΔVOD) 9 5.12 LVDS Output Short-Circuit Current (IOSL) 10 5.13 Power Off Output Leakage Current (IO-OFF) 11 5.14 LVDS Output High Impedance Current (IOZL) 12 5.15 Built-in Differential Input Resistance (RIT) 13 5.16 Built-in Differential Output Resistance (ROT) 13 5.17 Static Supply Current (IDD) 14 5.18 Turning Off the Supply Current (IDDZ) 15 6 Dynamic Parameter Test 16 6.1 Input Capacitor (CI) and Output Capacitor (CO) 16 6.2 Dynamic Supply Current (IDDA) 18 6.3 Maximum operating frequency (fMAX) 18 6.4 Minimum operating frequency (fMIN) 19 6.5 Maximum Data Rate (DRMAX) 20 6.6 Output from Low Level to High Level Transmission Delay (tPLH) 20 6.7 Output High to Low Transmission Delay (tPHL) 22 6.8 Output Transmission Delay from High-Z to High-Level (tPZH) 22 6.9 Output from High Impedance to Low Transmission Delay (tPZL) 24 6.10 Output from High Level to High Impedance Transmission Delay (tPHZ) 24 6.11 Output from Low Level to High Impedance Transmission Delay (tPLZ) 25 6.12 Output Transition from Low Level to High Level (tTLH) 25 6.13 Output Transition from High Level to Low Level (tTHL) 27 6.14 Pulse Skew (tSKP) 27 6.15 Interchannel Time Lag (tSKO) 28 6.16 Eye height (eH) 28 6.17 Eye Width (eW) 29 6.18 Deterministic jitter (Dj) 30 6.19 Random Jitter (Rj) 30 6.20 Total Jitter 31 Appendix A (Informative Appendix) Eye Diagram Test Instrument Requirements 32

Foreword

This standard was drafted in accordance with the provisions given in GB/T 1.1-2009. Please note that some of the contents of this document may involve patents. The issuing agency of this document does not assume responsibility for identifying these patents. This standard was proposed by the Ministry of Industry and Information Technology of the People's Republic of China. This standard is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78). This standard was drafted by. Chengdu Zhenxin Science and Technology Co., Ltd., the Ministry of Industry and Information Technology, the Institute of Electronics Industry Standardization, and Industrial Letters. Information Technology Research Institute, Shenzhen State Microelectronics Co., Ltd., Shenzhen Zhongzhi United Electronics Co., Ltd., China Electronics Technology Group The twenty-ninth institute of the company. The main drafters of this standard. Chen Yan, Luo Bin, Guo Chao, Wang Huiying, Li Xin, Cai Zhigang, Yan Haizhong, Zhong Ke. Semiconductor integrated circuit Low voltage differential signal circuit test method

1 Scope

This standard specifies a low voltage differential signaling (LVDS) circuit for semiconductor integrated circuits ( The basic principle of the static parameter and dynamic parameter test method is called "device". This standard applies to the test of static parameters and dynamic parameters of low-voltage differential signal circuits.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this article Pieces. For undated references, the latest version (including all amendments) applies to this document. GB/T 17574-1998 Semiconductor device integrated circuit Part 2. Digital integrated circuits

3 Terms and definitions

The following terms and definitions apply to this document. 3.1 Pulse delay pulsekew In the same channel, the transmission delay time from the low level to the high level and the transmission delay time from the high level to the low level are output. Difference. 3.2 Channel-to-channel skew between channels For multi-channel devices, the difference in transmission delay between different channels. 3.3 Eye diagram eyediagram The result of superimposing and displaying the bit stream of the collected serial signal is cumulatively accumulated in the afterglow manner, and the superimposed figure is an eyelet shape. 3.4 Eye height eyediagramheight The amplitude of the eye opening in the vertical direction. 3.5 Eye width eyediagramwidth The amplitude of the eye opening in the horizontal direction. 3.6 Jitter jitter The short-term deviation of the signal at a certain moment relative to its ideal time position. 3.7 Deterministic jitter deterministic jitter Due to the identifiable interference signal, the amplitude of the jitter is limited and has non-random causes. ......

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Tips & Frequently Asked Questions:

Question 1: How long will the true-PDF of GB/T 35007-2018_English be delivered?

Answer: Upon your order, we will start to translate GB/T 35007-2018_English as soon as possible, and keep you informed of the progress. The lead time is typically 3 ~ 5 working days. The lengthier the document the longer the lead time.

Question 2: Can I share the purchased PDF of GB/T 35007-2018_English with my colleagues?

Answer: Yes. The purchased PDF of GB/T 35007-2018_English will be deemed to be sold to your employer/organization who actually pays for it, including your colleagues and your employer's intranet.

Question 3: Does the price include tax/VAT?

Answer: Yes. Our tax invoice, downloaded/delivered in 9 seconds, includes all tax/VAT and complies with 100+ countries' tax regulations (tax exempted in 100+ countries) -- See Avoidance of Double Taxation Agreements (DTAs): List of DTAs signed between Singapore and 100+ countries

Question 4: Do you accept my currency other than USD?

Answer: Yes. If you need your currency to be printed on the invoice, please write an email to Sales@ChineseStandard.net. In 2 working-hours, we will create a special link for you to pay in any currencies. Otherwise, follow the normal steps: Add to Cart -- Checkout -- Select your currency to pay.